A Formal Study of Power Variability Issues and Side-Channel Attacks for Nanoscale Devices

Abstract

Abstract. Variability is a central issue in deep submicron technologies, in which it becomes increasingly difficult to produce two chips with the same behavior. While the impact of variability is well understood from the microelectronic point of view, very few works investigated its significance for cryptographic implementations. This is an important concern as 65-nanometer and smaller technologies are soon going to equip an increasing number of security-enabled devices. Based on measurements performed on 20 prototype chips of an AES S-box, this paper provides the first comprehensive treatment of variability issues for side-channel attacks. We show that technology scaling implies important changes in terms of physical security. First, common leakage models (e.g. based on the Hamming weight of the manipulated data) are no longer valid as the size of transistors shrinks, even for standard CMOS circuits. This impacts both the evaluation of hardware countermeasures and formal works assuming that independent computations lead to independent leakage. Second, we discuss the consequences of variability for profiled side-channel attacks. We study the extend to which a leakage model that is carefully profiled for one device can lead to successful attacks against another device. We also define the perceived information to quantify this context, which generalizes the notion of mutual information with possibly degraded leakage models. Our results exhibit that existing side-channel attacks are not perfectly suited to this new context. They constitute an important step in better understanding the challenges raised by future technologies for the theory and practice of leakage resilient cryptography.

Behind the Scene of Side Channel Attacks

“…attacks mechanisms and targeted platforms. This approach and our final purpose are close to those in the works of Standaert et al [33] and Renauld et al [29].…”

“…We report here on these experiments results. We moreover use them to confirm and complete the interesting behaviours observed in [29]: (1) the leakage seems to diverge from the classical Hamming weight model as the CMOS technology tends to the nanometer scale, which makes LRA a promising tool for side channel evaluations of nano-scale devices and (2) TA is effective in practice, even when the templates are built on one copy of the device and the attack is done on another copy.…”

“…Subsequent works have then been published which either show how to apply them against particular implementations (e.g. AES, RSA or ECDSA) or propose efficiency/effectiveness improvements [1,3,27,29]. In [27], the authors reduce the complexity of template attacks by first applying a pre-processing on the measurements (to go from time domain to frequency domain) and then by applying dimension reduction techniques (e.g.…”

“…For such a model, we have the following well known question 10 about the efficiency of template attack: how sound/relevant is a profiling done on a device A when attacking another device B ? The first work, and to the best of our knowledge, the single one reporting on template attacks in such context is due to Renauld et al [29]. On the latter article, the two devices used for the experiments are test chips implementing an AES s-box and made in 65-nanometer CMOS technology.…”

“…In spite of the evidence of this observation, it is rarely taken into account when analysing the effectiveness of a side channel attack. Such an analysis is indeed frequently done under the assumption, sometimes implicit, that a small number of points of interest (POI) has already been extracted from the traces either by pattern matching [21], or by dimension reduction [1,6,7,32] or thanks to a previous successful attack [10,29]. However, the two first categories of techniques are not yet perfect and, after reduction, the traces are often still composed of several points in practice.…”