A formal technique for hardware interface design

Baganne, Adel; Philippe, Jean; Martin, Éric

doi:10.1109/82.673640

Cited by 19 publications

(8 citation statements)

References 11 publications

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“…We summarise the related works as follows. The authors use a wide variety of the design techniques, such as graph-based ones (Madsen and Hald, 1995;Chou et al, 1995), formal methods (Baganne et al 1997), automata theory (Smith and Micheli, 1998;Passerone et al, 1998), Petri nets (Lysecki and Vahid, 2002), grammar-based approaches (Öberg et al, 1996;Siegmund and Mueller, 2000) and object-oriented techniques (Vahid and Tauro, 1997) to implement the interface synthesis. Some authors use the generative techniques (e.g., Siegmund and Mueller (2000) apply code templates to generate interface controllers).…”

Section: Discussionmentioning

confidence: 99%

“…Given a functional description of component ports and detailed timming, operational, and data width information, the device drivers that enable HW/SW communication are generated. Baganne et al (1997) describe a formal technique to communication synthesis for HW/SW co-design systems. A communication interface is generated at the same time as the HW module by a high-level synthesis tool.…”

Section: System-level Interface Synthesismentioning

confidence: 99%

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Wrapping of Soft IPs for Interface‐based Design Using Heterogeneous Metaprogramming

Damaševičius¹,

Štuikys²

2003

Informatica

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We discuss the application of heterogeneous metaprogramming (MPG) for the interfacebased design, which deals with the synthesis of the communication interfaces between Intellectual Property components (IPs). Heterogeneous MPG is based on the simultaneous usage of a domain language for describing domain functionality and a metalanguage for developing generic components and program generators. We present a design framework based on the MPG techniques. The novelty of our approach is that we apply the concept of heterogeneous MPG for the automatic generation of IP wrappers for communication between the third-party soft IPs systematically. We present a case study for the synthesis of the communication interfaces using a FIFO protocol.

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Section: Discussionmentioning

confidence: 99%

Section: System-level Interface Synthesismentioning

confidence: 99%

Wrapping of Soft IPs for Interface‐based Design Using Heterogeneous Metaprogramming

Damaševičius¹,

Štuikys²

2003

Informatica

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“…In [2], by searching and isolating compatibility cliques in an undirected graph, the authors identify the different storage structures (FIFO or LIFO). This approach has four main drawbacks: (1) identifying a maximum clique in an undirected graph is a NPcomplete problem (resource identification step), (2) when such a clique is found, analysis have to be performed to define the clique type (FIFO or LIFO) and to check if the I/O constraints are respected (resource identification step), (3) the proposed flow does not allow sizing of identified storage elements (resource sizing step) and (4) the authors do not propose any exploration algorithm (resource binding step).…”

Section: B Storage Element Bindingmentioning

confidence: 99%

“…This solution enables the implementation of nondeterministic communications, but it does not allow minimizing of the adapter overhead since overlapping of input and output data is not possible. In [2], a formal technique for hardware interface design is proposed. A generic interface model targeted by the communication synthesis is used.…”

Section: Introductionmentioning

confidence: 99%

A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver

Coussy¹,

Urard

Martin³

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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ISBN:1-4244-0921-7International audienceThis paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a Resource Constraints Graph (RCG). The RCG properties enable an efficient architecture space exploration in order to synthesize a STAR component. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver

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“…This solution enables the implementation of non-deterministic communications, but there is no optimization of the adapter overhead since overlapping of input and output data is not possible. In [2], a formal technique for hardware interface design is proposed. A generic interface model targeted by the communication synthesis is used.…”

Section: Introductionmentioning

confidence: 99%

A design methodology for space-time adapter

Coussy¹,

Urard

Martin

2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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This paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graphtheoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism…), and formalizes communication constraints through a Resource Constraints Graph (RCG). The RCG properties enable an efficient architecture space exploration in order to synthesize a STAR component. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver.

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A formal technique for hardware interface design

Cited by 19 publications

References 11 publications

Wrapping of Soft IPs for Interface‐based Design Using Heterogeneous Metaprogramming

Wrapping of Soft IPs for Interface‐based Design Using Heterogeneous Metaprogramming

A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver

A design methodology for space-time adapter

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