A Fractional-N PLL for SONET-Quality Clock-Syntlhesis Applicationis

Abstract

of the AZ modulator calculates the expected phase error R. Hulfachor2, D. Pastorello2, R. Juhn2 (no extra hardware required). This value, D, has to be converted into a charge, Qa, that matches the charge, Qcp, we expect from 'Silicon Laboratories, Austin, TX, 2Silicon Laboratories, Nashua, NH the charge pump. Specifically, Traditionally precision clock sources have been implemented by Qcp = A tvco Iep= Qa = tDAc f using precision resonators such as quartz crystals or SAW res-Therefore I. and I should be derived from the same source. tDAc onators. In high-performance PLLs, VCXOs or voltage-control must be a ti reflated t in e 4 cycles), so tmac r svrrs* . vrr vIf _ k implementations.* mutba time related to tl;0 (inL our case 4 cycles), so that mnatch-SAW oscillators (VCSOs) have been used. These ing to about 5% can be achieved. The DAC implementation has rely on the ability to accurately manufacture a precise resonator 128 identical elements and 2 scaled sources. A return-to-zero confor a given frequency, using simple circuitry to entice the oscillastraint reducing nonlinearity is inherent in the operation. DEM tion. It is much easier from a manufacturing-flow and processcontrol perspective to fabricate low-accuracy (but high-Q) fixedfrequency resonators, but this places the difficulty in the frequency synthesis. Fractional-N PLLs are a well-known technique to In order to rgeduce the noise contribution fhom the phase-detector synthesize frequencies with arbitrary precision from a fixed-fre-ADC (Fig. 2.94), a small full-scale value is chosen, thereby reducquency reference clock. This property makes them attractive for ing quantization error. The full scale is actually less than the use with fixed timing sources such as crystal oscillators and pak inputpaser expcted. Thisis pse beause low-VCXs While the bai ide is sipe th ke to a successfu pass signal transfer function is built into the ADC. The first input impleentaion ofe basic frequen synple,thesize isy in managi s j capacitor serves as a current summing node as well as part of the adpurmentiou formanc T snte is tandmard fo e a i me lowest frequency pole of the ADC signal transfer function. More has sprom o efo he mtrn NtEiT reire for cxamploc substantial noise shaping is achieved by the 2 integrators that follow. A large nonlinear capacitance iS present at the input to the sources. A frequency-synthesis IC targeted to replace high-frec Alag nin capacitance is presna the input torthe qu ncyX an VCXOs is prpsd JTte pefrac in th OC-current ADC. This capacitance is duLe to the charge-puLmp cuLrrent quency XO and VCX*s is proposed. Jitter performance *n the OCsources and the DAC current sources. Unlike an RC filter in front 192 band, integrated from 5OkHz to 80MHz, is 0P3s,,,s and the of the ADC, embedding the LPF function in the ADC holds the current draw excluding the output driver is 70mA. nonlinear capacitance at virtual ground, removing its effect.An overview of the chip architecture is shown in Fig. 2.9.1. A crys-Phase-noise plots of the system in 5 differen...

A novel fractional-N PLL based on a simple reference multiplier

“…Overlapping clocks were created between the complimentary UP and DN pulses to ensure a continuous flow of current. The cascode devices provide a good isolation between the CP plus and minus nodes [5]. In addition, a buffer is used to balance the CP output with the dummy branch, which prevent charge sharing from the dumm y side.…”

“…In a popular approach, a dL modulator is used to approximate the desired fractional ratio with a sequence of integers such that over time a fractional multiple of the reference frequency can be synthesized [1]- [5]. As a result the loop achieves steady state by aligning the time average of the divided clock to the reference clock, but the true instantaneous clock edges are never aligned.…”

Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL

“…Ohmic switches driven by overlapping clocks were used to avoid the fast switching of bias signals which typically occur for switches used in saturation. Cascode devices provide isolation between CP plus and minus nodes [7]. A buffer is used to balance the CP output node with the dummy node.…”