Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL

Abstract

The loop bandwidth of fractional-N PLL is a desirable parameter for many wireless communication applications. To improve bandwidth design tradeoffs must be made among different circuit blocks. The key to successful implementation of a wideband fractional-N synthesizer is in managing jitter and spurious performance. In this paper we compare several techniques for bandwidth enhancement including an improved version of one recently proposed by the authors. Circuits that suppress fractional spurs along the signal path are discussed. Simulations results from Matlab/Simulink are also presented. IEEE Computer Society Annual Symposium on VLSI978-0-7695-3170-0/08 $25.00