A framework for design space exploration of resource efficient network processing on multiprocessor SoCs

Grünewald, Matthias; Niemann, Jörg-Christian; Porrmann, Mario; Rückert, Ulrich

doi:10.1016/b978-012088476-6/50013-7

Cited by 3 publications

(5 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Packet processing of one node is not simulated, but executed on the MPSoC architecture. The hardware is connected to the simulator using the hardware abstraction layer (HAL) of the packet processing library, which has been presented in Grünewald et al (2005a). The HAL also ensures the synchronization of the hardware and the simulator.…”

Section: Prototyping Environmentmentioning

confidence: 99%

“…Packet based communication is used instead of simple time multiplexing, enabling a high bandwidth utilization. In Grünewald et al (2005a) methods have been proposed to assign the protocol functions to processors and to estimate the resource consumption of the final mapping. During the mapping either delay or energy consumption per packet can be minimized.…”

Section: The Network-on-chipmentioning

confidence: 99%

“…To determine the resource efficiency of the software and of the hardware implementation, our VHDL-based characterisation environment PERFMON is used (Grünewald et al, 2005a). PERFMON provides an infrastructure for simulation and evaluation of the whole system, including main memory, debugging units, and performance counters.…”

Section: The Processing Elementmentioning

confidence: 99%

“…In our work, we evaluate Multiprocessor System-onChips (MPSoC) instead of single processors with higher clock frequency to achieve the required performance and resource efficiency. The MPSoC comes with an application specific``Network-on-Chip (NoC)´´that offers a high bandwidth and guranteed latency (Grünewald et al, 2005a). The protocol functions of the application are automatically…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Realtime multiprocessor for mobile ad hoc networks

et al. 2008

View full text Add to dashboard Cite

Abstract. This paper introduces a real-time Multiprocessor System-On-Chip (MPSoC) for low power wireless applications. The multiprocessor is based on eight 32bit RISC processors that are connected via an Network-On-Chip (NoC). The NoC follows a novel approach with guaranteed bandwidth to the application that meets hard realtime requirements. At a clock frequency of 100 MHz the total power consumption of the MPSoC that has been fabricated in 180 nm UMC standard cell technology is 772 mW.

show abstract

Section: Prototyping Environmentmentioning

confidence: 99%

Section: The Network-on-chipmentioning

confidence: 99%

Section: The Processing Elementmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Realtime multiprocessor for mobile ad hoc networks

et al. 2008

View full text Add to dashboard Cite

show abstract

“…Data is transmitted by means of packet fragments called flits (Flow Control Digits) that represent the atomic on-chip data transmission unit. We have already successfully applied several application scenarios to this architecture as outlined in [8][9][10] [12]. For the first hardware implementation we have chosen a mesh, due to efficient hardware integration.…”

Section: Examplary Implementation Of a Cmp -The Giganetic Architecturementioning

confidence: 99%

Analytical approach to massively parallel architectures for nanotechnologies

Jager

Niemann

Rückert

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)

View full text Add to dashboard Cite

In the emerging field of single-chip multiprocessors (CMP) analytical models of performance and power consumption are necessary for design space exploration and the analysis of existing architectures. In the light of ever decreasing structure sizes in microchips the scalability of proposed CMPs is of great interest to the developers. Looking even further into the future at the possibilities offered by, e. g., nanotechnology, a set of such models may help to identify promising architectures and possible bottlenecks even before the enabling technologies exist. In this paper, we present our current work in this area in the form of two models. The first and very basic model is based on Amdahl's law and gives a first promising outlook on chip multiprocessing. Based on the more complex BSP model our second model takes the on-chip communication into account and thus allows a much more detailed look at the architecture. In both cases, basic laws of circuit technology have been combined with the underlying models that now take the effects of device scaling into account. Later we will also present the GigaNetIC 1 architecture, a CMP developed by our research group. It will then be analyzed by applying the BSP-based model.

show abstract

Increasing the Resource-Efficiency of the CSMA/CA Protocol in Directional Ad Hoc Networks

Grünewald

Rückert

2005

Ad-Hoc, Mobile, and Wireless Networks

View full text Add to dashboard Cite

A framework for design space exploration of resource efficient network processing on multiprocessor SoCs

Cited by 3 publications

References 19 publications

Realtime multiprocessor for mobile ad hoc networks

Realtime multiprocessor for mobile ad hoc networks

Analytical approach to massively parallel architectures for nanotechnologies

Increasing the Resource-Efficiency of the CSMA/CA Protocol in Directional Ad Hoc Networks

Contact Info

Product

Resources

About