Today's deep submicron fabrication technologies enable design engineers to put an impressive number of components like microprocessors, memories, and interfaces on a single microchip. With the emergence of 100 nm processes, billions of transistors can be integrated on one die and form a parallel system, consisting out of housands of components. To handle this impressive number of components it is important to provide a communication infrastructure which is able to scale with the capabilities of upcoming fabrication technologies and which provides the foundation for efficient on-chip communication protocols. This paper addresses the architectural requirements which are coupled with the transfer of well known techniques from parallel computers onto the design of SoCs and proposes an on-chip architecture which is based on active switch boxes. We will show that this architecture is able to fill the existing design gap between an efficient use of the design space and the design complexity with reasonable resource requirements

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The GigaNetIC project aims to develop high-speed components for networking applications based on massively parallel architectures. A central part of this project is the design, evaluation, and realization of a parameterizable network processing unit. In this paper we present a design methodology for network processors which encompasses the research areas from the application software down to the gate level of the chip. Key components of this holistic approach have been successfully applied to characteristic examples of architecture refinements.

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