Today's deep submicron fabrication technologies enable design engineers to put an impressive number of components like microprocessors, memories, and interfaces on a single microchip. With the emergence of 100 nm processes, billions of transistors can be integrated on one die and form a parallel system, consisting out of housands of components. To handle this impressive number of components it is important to provide a communication infrastructure which is able to scale with the capabilities of upcoming fabrication technologies and which provides the foundation for efficient on-chip communication protocols. This paper addresses the architectural requirements which are coupled with the transfer of well known techniques from parallel computers onto the design of SoCs and proposes an on-chip architecture which is based on active switch boxes. We will show that this architecture is able to fill the existing design gap between an efficient use of the design space and the design complexity with reasonable resource requirements

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This paper presents a special photodiode array layout to be used in optical pickup units in combination with optical storage systems. Apart from the features that a standard array offers, this design enables higher resolution of the data recovery diodes. Furthermore, additional diodes for the determination of the spatial light intensity are included. The special layout of the array ensures crosstalk isolation and linearizes the spectral response of the data recovery diodes enabling less circuitry needed for the readout of the photocurrent. The structure was fabricated in standard 0.6µm twin well CMOS technology.