On-chip interconnects for next generation system-on-chips

Brinkmann, André; Niemann, Jörg-Christian; Hehemann, I.; Langen, Dominik; Porrmann, Mario; Rückert, Ulrich

doi:10.1109/asic.2002.1158058

Cited by 22 publications

(10 citation statements)

References 12 publications

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“…One category of existing simulation techniques (e.g., [6,7,[9][10][11][12]) employ statistical packet generation models such as random and on-off to generate interconnect traffic and thus abstract computation using data packet-generators. Such frameworks may not be able to capture true communication behavior in an application and often fail to capture (or might introduce false) worst-case behavior in the communication network.…”

Section: Preliminaries and Related Workmentioning

confidence: 99%

A Flexible Framework for Communication Evaluation in SoC Design

Kalla

Henkel³

2008

Int J Parallel Prog

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Multi-core System-on-Chips (SoCs) with on-chip networks are becoming a reality after almost a decade of research. One challenge in developing such SoCs is the need of efficient and accurate simulators for design space exploration. This paper addresses this need by presenting SoCExplore, a framework for fast communication-centric design space exploration of complex SoCs with network-based interconnects. Efficiency is achieved through abstraction of computation as a high-level trace, while accuracy is maintained through cycle-accurate interconnect simulation. The flexibility offered allows for fast partition/mapping and interconnect design space exploration. In a case study, a speed-up of 94% over architectural simulation is obtained for the MPEG application. A critical evaluation of the capabilities of our (or any trace based) framework is also provided.

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Section: Preliminaries and Related Workmentioning

confidence: 99%

A Flexible Framework for Communication Evaluation in SoC Design

Kalla

Henkel³

2008

Int J Parallel Prog

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“…The architecture presented in [14] takes the opposite approach and uses a hierarchical interconnect to link multiple bus-based SoCs together.…”

Section: Related Workmentioning

confidence: 99%

A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing

Bourduas

Žilić

2007

First International Symposium on Networks-on-Chip (NOCS'07)

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Abstract-A popular network topology for Network-on-Chip (NoC) implementations is the two-dimensional mesh. A disadvantage of the mesh topology is in its large communication radius. By partitioning a two-dimensional mesh into several sub-meshes and connecting them using a global interconnect, we can reduce the average number of hops for global traffic. This paper presents a hybrid architecture that partitions a large 2D-mesh into several smaller sub-meshes which are globally connected using a hierarchical ring interconnect. Hierarchical rings have been selected for study because of their simplicity, speed and efficiency in embedding onto a circuit layout, as well as for their suitability for efficient cache coherent protocols. An original SystemC modeling platform was implemented in order to compare the traditional 2D-mesh with the hybrid ring/mesh architectures and the simulation results will show that our hybrid architecture does indeed have a positive effect on the average hop count.

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“…fig. 4) is the GigaNoC [19], a hierarchical hybrid network on chip (NoC) [5][6] [30]. Local on-chip busses are used to connect small numbers of processing elements (PEs) [18][11] [7].…”

Section: Examplary Implementation Of a Cmp -The Giganetic Architecturementioning

confidence: 99%

Analytical approach to massively parallel architectures for nanotechnologies

Jager

Niemann

Rückert

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)

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In the emerging field of single-chip multiprocessors (CMP) analytical models of performance and power consumption are necessary for design space exploration and the analysis of existing architectures. In the light of ever decreasing structure sizes in microchips the scalability of proposed CMPs is of great interest to the developers. Looking even further into the future at the possibilities offered by, e. g., nanotechnology, a set of such models may help to identify promising architectures and possible bottlenecks even before the enabling technologies exist. In this paper, we present our current work in this area in the form of two models. The first and very basic model is based on Amdahl's law and gives a first promising outlook on chip multiprocessing. Based on the more complex BSP model our second model takes the on-chip communication into account and thus allows a much more detailed look at the architecture. In both cases, basic laws of circuit technology have been combined with the underlying models that now take the effects of device scaling into account. Later we will also present the GigaNetIC 1 architecture, a CMP developed by our research group. It will then be analyzed by applying the BSP-based model.

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On-chip interconnects for next generation system-on-chips

Cited by 22 publications

References 12 publications

A Flexible Framework for Communication Evaluation in SoC Design

A Flexible Framework for Communication Evaluation in SoC Design

A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing

Analytical approach to massively parallel architectures for nanotechnologies

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