A Scalable Parallel SoC Architecture for Network Processors

Niemann, Jörg-Christian; Porrmann, Mario; Rückert, Ulrich

doi:10.1109/isvlsi.2005.13

Cited by 13 publications

(3 citation statements)

References 8 publications

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“…Fu and Hagsand [17] have studied current network processors and introduced a network processor model. Niemann et al [18] have presented architecture for NPs that was based on a uniform, massively parallel structure. They reused predefined IP building blocks.…”

Section: Related Workmentioning

confidence: 99%

A Design of Intel’s IXP Meant for Embedded Systems

Jain¹,

Jain²

2019

IJRTE

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Technologies to design an embedded system can be of three types: processor technology, IC technology & design technology. Billions of computing systems are built every year for a variety of purpose. They are built within larger electronic devices. These systems perform a one particular function on regular basis. These systems do not recognized by the device's user. These systems are known as embedded system. Broad categories for system implementation are: Application Specific Integrated Circuit, Field Programmable Gate Array, Co-Processor, Application Specific Instruction Processor and General Purpose Processor. From the network processor's designing point of view, it is very important to understand the preliminary characteristics of network applications which are generally based on address lookup, pattern matching, and queuing management which is further classified as Control plane and Data Plane processing. Keywords: Network Processor, General Purpose processor, Field programmable gate array.I.

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Section: Related Workmentioning

confidence: 99%

A Design of Intel’s IXP Meant for Embedded Systems

Jain¹,

Jain²

2019

IJRTE

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“…The need for energy‐efficient processors led to the development of low‐power many‐core architectures. Early studies such as the GigaNetIC , the CHNoC , and the MCNoC focused on NoC aspects. Currently, cluster‐based architectures are under development such as the SMYLEref many‐core and a cluster‐based multi‐core SoC .…”

Section: Related Workmentioning

confidence: 99%

CAP Bench: a benchmark suite for performance and energy evaluation of low‐power many‐core processors

Souza

Penna

Queiroz

et al. 2016

Concurrency and Computation

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International audienceSUMMARY The constant need for faster and more energy-efficient processors has been stimulating the development of new architectures, such as low-power many-core architectures. Researchers aiming to study these architectures are challenged by peculiar characteristics of some components such as Networks-on-Chip and lack of specific tools to evaluate their performance. In this context, the goal of this paper is to present a benchmark suite to evaluate state-of-the-art low-power many-core architectures such as the Kalray MPPA-256 low-power processor, which features 256 compute cores in a single chip. The benchmark was designed and used to highlight important aspects and details that need to be considered when developing parallel applications for emerging low-power many-core architectures. As a result, this paper demonstrates that the benchmark offers a diverse suite of programs with regard to parallel patterns, job types, communication intensity and task load strategies, suitable for a broad understanding of performance and energy consumption of MPPA-256 and upcoming many-core architectures

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“…fig. 4) is the GigaNoC [19], a hierarchical hybrid network on chip (NoC) [5][6] [30]. Local on-chip busses are used to connect small numbers of processing elements (PEs) [18][11] [7].…”

Section: Examplary Implementation Of a Cmp -The Giganetic Architecturementioning

confidence: 99%

Analytical approach to massively parallel architectures for nanotechnologies

Jager

Niemann

Rückert

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)

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In the emerging field of single-chip multiprocessors (CMP) analytical models of performance and power consumption are necessary for design space exploration and the analysis of existing architectures. In the light of ever decreasing structure sizes in microchips the scalability of proposed CMPs is of great interest to the developers. Looking even further into the future at the possibilities offered by, e. g., nanotechnology, a set of such models may help to identify promising architectures and possible bottlenecks even before the enabling technologies exist. In this paper, we present our current work in this area in the form of two models. The first and very basic model is based on Amdahl's law and gives a first promising outlook on chip multiprocessing. Based on the more complex BSP model our second model takes the on-chip communication into account and thus allows a much more detailed look at the architecture. In both cases, basic laws of circuit technology have been combined with the underlying models that now take the effects of device scaling into account. Later we will also present the GigaNetIC 1 architecture, a CMP developed by our research group. It will then be analyzed by applying the BSP-based model.

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A Scalable Parallel SoC Architecture for Network Processors

Cited by 13 publications

References 8 publications

A Design of Intel’s IXP Meant for Embedded Systems

A Design of Intel’s IXP Meant for Embedded Systems

CAP Bench: a benchmark suite for performance and energy evaluation of low‐power many‐core processors

Analytical approach to massively parallel architectures for nanotechnologies

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