A framework for FPGA acceleration of large graph problems: Graphlet counting case study

Abstract

In many application domains, data are represented using large graphs involving millions of vertices and edges. Graph analysis algorithms, such as finding short paths and isomorphic subgraphs, are largely dominated by memory latency. Large cluster-based computing platforms can process graphs efficiently if the graph data can be partitioned, and on a smaller scale partitioning can be used to allocate graphs to low-latency onchip RAMs in reconfigurable devices. However, there are many graph classes, such as scale-free social networks, which lack the locality to make partitioning graph data an efficient solution to the latency problem and are far too large to fit in onchip RAMs and caches. In this paper, we present a framework for reconfigurable hardware acceleration of these large-scale graph problems that are difficult to partition and require highlatency off-chip memory storage. Our reconfigurable architecture tolerates off-chip memory latency by using a memory crossbar that connects many parallel identical processing elements to shared off-chip memory, without a traditional cached memory hierarchy. Quantitative comparison between the software and hardware performance of a graphlet counting case-study shows that our hardware implementation outperforms a quad-core software implementation by 10 times for large graphs. This speedup includes all software and IO overhead required, and reduces execution time for this common bioinformatics algorithm from about 2 hours to just 12 minutes. These results demonstrate that our methodology for accelerating graph algorithms is a promising approach for efficient parallel graph processing.

Engineering a Delegatable and Error-Tolerant Algorithm for Counting Small Subgraphs

“…For a nonexhaustive sample of the extensive body of work in this direction, including theoretical and engineering work, cf. [108,92,111,68,29,64,107,36,3,47,73,97,74,88,18,45,24,91,96,63,93,4,25,90]. Our work differs from these works in that we seek a proof-of-concept implementation for simultaneous delegatability and errortolerance.…”

FPGA acceleration of semantic tree reasoning algorithms

“…For example, [2] elaborates a framework for large graph manipulation in hardware. Graph data, which cannot be partitioned and locally processed, is stored lineally in off-chip memories.…”

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

“…While the prototypes described in [Canis et al, 2013;Chung et al, 2012;Cong and Xiao, 2013;Ismail and Shannon, 2011;Lysecky and Vahid, 2009;Pilato et al, 2012;Vassiliadis et al, 2004;Willenberg and Chow, 2013] implement the host and the kernels on the same chip (embedded hardwired or soft processor as the host), the implementation of [Benini et al, 2012;Betkaoui et al, 2011;Convey Computer, 2012;Ling et al, 2009;Putnam et al, 2014;Schumacher et al, 2012;Stuecheli, 2013;Voros et al, 2013] uses different chips for the host and the kernels.…”

“…The P2012 architecture [Benini et al, 2012] • Shared memory: Shared memory is used in many commercial hardware accelerator systems for high performance computing. Intel proposes a system using a Front Side Bus (FSB) [Ling et al, 2009] • Crossbar: The research in [Betkaoui et al, 2011] proposed a framework for accelerating large graph problems. The target system includes graph processing elements (GPEs) connected with memory modules through a full crossbar.…”