A framework for hardware-based DVFS management in multicore mixed-criticality systems

Haririan, Parham; García-Ortiz, Alberto

doi:10.1109/recosoc.2015.7238090

Cited by 6 publications

(10 citation statements)

References 10 publications

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“…Section 5 reviews a case in which complex embedded systems-running mixed-criticality tasks-are explored via a virtual framework equipped with a run-time power management mechanism. The work in [45] exploits the simulation framework proposed by [3] and extends it to demonstrate a hardware-controlled run-time energy management technique for mixed-criticality tasks. It reports notable power savings using its method.…”

Section: Dvfs Support Within Simulation Platformsmentioning

confidence: 99%

“…Section 3 explained that simulation provides more implementation details than analytical modeling. The work in [45] demonstrates how the hardware-managed DVFS simulation framework (Section 3) can be used for energy-efficient design exploration of mixed-criticality systems. The next section presents a summary of this work.…”

Section: Mixed Criticality and Energy Efficiencymentioning

confidence: 99%

“…Only three works were found in the literature so far, that integrate power management mechanisms (specifically DVFS) within virtual prototyping platforms that originally did not support DVFS [1][2][3]. One work-which is in fact an extension of [3]-studies DVFS for mixed-criticality systems using architectural simulation and is selected as the case review in this article [45]. Here, it is explained how the hardware-managed DVFS framework reviewed in Section 3 is used to demonstrate an energy-efficient mixed-criticality system in one step ahead of analytical modeling: architectural simulation.…”

Section: Case Reviewmentioning

confidence: 99%

“…Note that a violation in LO-mode leads to switch to HI-mode in which the DVFS manager plays no roles (mode switch protocol-see Section 4.3). Hardware-managed DVFS architecture for mixed-criticality systems adopted from [45].…”

mentioning

confidence: 99%

“…In addition, it considers the run-time information arriving from health monitoring modules to make the scaling decision. The work in [45] models its experimental mixed-criticality system through architectural simulation and reports 24.6% saving in power consumption using its proposed approach with no rise in heartbeat violations. Hardware-managed DVFS architecture for mixed-criticality systems adopted from [45].…”

mentioning

confidence: 99%

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DVFS and Its Architectural Simulation Models for Improving Energy Efficiency of Complex Embedded Systems in Early Design Phase

Haririan

2020

Computers

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Dealing with resource constraints is an inevitable feature of embedded systems. Power and performance are the main concerns beside others. Pre-silicon analysis of power and performance in today’s complex embedded designs is a big challenge. Although RTL (Register-Transfer Level) models are more precise and reliable, system-level modeling enables the power and performance analysis of complex and dense designs in the early design phase. Virtual prototypes of systems prepared through architectural simulation provide a means of evaluating non-existing systems with more flexibility and minimum cost. Efficient interplay between power and performance is a key feature within virtual platforms. This article focuses on dynamic voltage and frequency scaling (DVFS), which is a well-known system-level low-power design technique together with its more efficient implementations modeled through architectural simulation. With advent of new computing paradigms and modern application domains with strict resource demands, DVFS and its efficient hardware-managed solutions get even more highlighted. This is mainly because they can react faster to resource demands and thus reduce induced overhead. To that end, they entail an effective collaboration between software and hardware. A case review in the end wraps up the discussed topics.

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Section: Dvfs Support Within Simulation Platformsmentioning

confidence: 99%

Section: Mixed Criticality and Energy Efficiencymentioning

confidence: 99%

Section: Case Reviewmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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DVFS and Its Architectural Simulation Models for Improving Energy Efficiency of Complex Embedded Systems in Early Design Phase

Haririan

2020

Computers

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Peak-Power Aware Life-Time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems

Navardi

Ranjbar

Rohbani

et al. 2022

IEEE Open J. Circuits Syst.

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Mixed-Criticality Systems (MCSs) include tasks with multiple levels of criticality and different modes of operation. These systems bring benefits such as energy and resource saving while ensuring safe operation. However, management of available resources in order to achieve high utilization, low power consumption, and required reliability level is challenging in MCSs. In many cases, there is a trade-off between these goals. For instance, although using fault-tolerance techniques, such as replication, leads to improving the timing reliability, it increases power consumption and can threaten life-time reliability. In this work, we introduce an approach named Life-time Peak Power management in Mixed-Criticality systems (LPP-MC) to guarantee reliability, along with peak power reduction. This approach maps the tasks using a novel metric called Reliability-Power Metric (RPM). The LPP-MC approach uses this metric to balance the power consumption of different processor cores and to improve the life-time of a chip. Moreover, to guarantee the timing reliability of MCSs, a fault-tolerance technique, called task re-execution, is utilized in this approach. We evaluate the proposed approach by a real avionics task set, and various synthetic task sets. The experimental results show that the proposed approach mitigates the aging rate and reduces peak power by up to 20.6% and 17.6%, respectively, compared to state-of-the-art.

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Run-time schedulability check of real-time tasks for energy efficiency

Haririan

García-Ortiz

2016

2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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A framework for hardware-based DVFS management in multicore mixed-criticality systems

Cited by 6 publications

References 10 publications

DVFS and Its Architectural Simulation Models for Improving Energy Efficiency of Complex Embedded Systems in Early Design Phase

DVFS and Its Architectural Simulation Models for Improving Energy Efficiency of Complex Embedded Systems in Early Design Phase

Peak-Power Aware Life-Time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems

Run-time schedulability check of real-time tasks for energy efficiency

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