A Frequency Synthesizer for LO in Millimeter-wave 5G Massive MIMO System

Kuai, Le; Wang, Hong; Chen, Jixin; Zhou, Houxin

doi:10.1109/apmc46564.2019.9038807

Cited by 6 publications

(2 citation statements)

References 5 publications

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“…The generated LO signal is output to a primary 1:8 Wilkinson power divider. The primary power divider splits the LO signal into eight secondary 1:8 power dividers with amplifiers to provide it to each row of transmitter/receiver modules [43]. The photograph of the LO circuit and the power divider is shown in Fig.…”

Section: Lo Generation and Power Divider Circuitmentioning

confidence: 99%

A N260 Band 64 Channel Millimeter Wave Full-Digital Multi-Beam Array for 5G Massive MIMO Applications

et al. 2020

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In this paper, a 37-42.5GHz (N260 Band) 64 channel full-digital multi-beam array for 5G massive multiple input multiple output (MIMO) applications is developed. The multi-beam array is built on a time division duplexing (TDD) architecture in which the transmitter and receivers are independent and working separately to enable more flexible channel configuration and hardware distribution. The 64 antenna elements of the array are aligned in a way that 16 elements lie in the horizontal and 4 in the vertical direction to deliver higher beam resolution in the horizontal plane. By using cables of unequal lengths, the 16×4 antenna elements are connected to a cluster of 8 × 8 transmitters/receivers. The hardware design of the transmitters, receivers, antennas and other circuits is demonstrated, with excellent measured RF performance achieved. Furthermore, the calibration of the massive MIMO array is presented, and the influence of inequality of array feedlines on calibration accuracy in a wide bandwidth is analyzed and experimentally verified. Finally, experimental studies on single beam scanning, multiple concurrent beam generation and over-the-air (OTA) performance of the transmitting and receiving array have been done. Simulation and measurement results suggest that the array has an excellent beam-forming capability that supports beam steering and generation of multiple concurrent beams. The OTA test reveals that the array can provide high modulation and demodulation accuracy for communication.

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Section: Lo Generation and Power Divider Circuitmentioning

confidence: 99%

A N260 Band 64 Channel Millimeter Wave Full-Digital Multi-Beam Array for 5G Massive MIMO Applications

et al. 2020

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“…Due to the low quality-factor of capacitors in mm-wave and CMOS (complementary metal-oxide-semiconductor) flicker noise, the phase noise of CMOS VCO is very poor and consumes a lot of power. Instead of running VCO at mm-wave, various combined structures of lower frequency SSPLL or ILPLL and following frequency multipliers have been preferred [5][6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

A Single-Stage 12-Times Frequency Multiplier for a 5G Frequency Synthesizer

Nam

Park

2022

J Electromagn Eng Sci

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This paper presents a single-stage 12-times frequency multiplier composed of an invented harmonic generator (HG) and a modified cascode buffer. The reliable output frequency band is guaranteed from 16 GHz to 28 GHz (54.5% frequency range). The whole band is divided to 256 subsidiary frequency bands by applying 8-bit digitally controlled capacitor banks of LC (inductor and capacitor)-tuned output. The invented HG architecture is based on a double-balanced mixer, but the bottom and top differential pairs are appropriately biased to generate the required turn-on time, τ , for obtaining the more dominant desired 12th harmonic. In addition, to reduce power consumption and conversion gain variation for the target frequency band, a negative-gm differential pair is added to the HG core in parallel to enhance the equivalent parasitic resistance, which is directly proportional to the HG gain. Newly created automatic constant amplitude control is able to keep the HG amplitude output constant as well as keep it from oscillating. Further desired harmonic amplification and unwanted suppression can be achieved by the proposed cascode buffer. The proposed 12-times multiplier is fabricated on a 65-nm CMOS (complementary metal-oxide-semiconductor) process and successfully tested. Chip die size is 0.4 mm2, and power consumption is only 4 mW.

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