A Full Code-Patterns Coverage High-Speed Embedded ROM Using Dynamic Virtual Guardian Technique

Chang, Meng-Fan; Chiou, Lih-Yih; Wen, Kuei-Ann

doi:10.1109/jssc.2005.862343

Cited by 14 publications

(15 citation statements)

References 20 publications

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“…In a read-0 operation, when V BL0 increases, V REF , begins to rise. Thus, V SM0 is larger for a given T SG than in a conventional sensing scheme [5].Combining DSSL and DASR schemes with weak BL-keepers enables our NAND-ROM to use higher V REF and shorter T SG for a given V SM1 and V SM0 than in a conventional scheme. The short T SG increases the operating speed and reduces dynamic power due to smaller average V BL0 across ROM-codes.…”

mentioning

confidence: 99%

A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications

Chang

Yang

Liang

et al. 2010

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

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Many low-voltage chips such as sensor networks and biomedical applications need large-capacity low-V DDmin -delay-product embedded ROM for storing fixed programs and data [1]. NOR-ROMs provide low V DD and high speed for smallcapacity applications with a short bitline (BL) [2]. However, if read-1 noise can be eliminated, a NAND-ROM is superior [1] for large-capacity storage in standby-dominated low-voltage chips because of smaller area, narrower cell-current (I CELL ) distribution, and lower standby current. Static NAND-ROM with short BL [1] achieves small read-1 noise and low V DD with a 33% area penalty. Applying selected precharge [3], driving source-line (SL) [4], or BL-shield [5], [6] schemes to NAND-ROM can eliminate only one of the read-1 noise sources, which are charge sharing, BL leakage, and BL crosstalk. The remaining read-1 noise reduces the sensing margins for reading 1-cells (V SM1 ) and 0-cells (V SM0 ) and limits the V DDmin and speed of NAND-ROMs. This paper presents dynamic split source-lines (DSSL) scheme to eliminate read-1 noise and a data-aware sensing reference (DASR) scheme to expand V SM0 to tolerate larger I CELL variations for large-capacity low-voltage NAND-ROM. These schemes enable largecapacity NAND-ROM to achieve lower V DDmin , higher speed, and lower power consumption with small area overhead. Figure 14.6.1 shows the structure of the DSSL and conventional metal-code NAND-ROM. The DSSL scheme employs two horizontal split SLs for the NANDchains (NDCs) in the same single sector, rather than a single common SL or vertical split SLs (for different columns [7]) in conventional arrays. Since there are no program and erase operations in a NAND-ROM, each NDC consists of k stacked NMOS bitcells and only one select-gate (SG), rather than the two SGs used in a NAND-Flash. As in conventional NAND-ROMs, all wordlines (WLs) are kept at V DD and all SG-lines (SGLs) are grounded in the precharge phase or standby mode. Unlike connecting to ground in conventional NAND-ROMs, all DSSL SLs are held at V DD . Since all bitcells are on in the precharge phase, all source/drain parasitic capacitors in each NDC are precharged to high, rather than grounded, as in a conventional NAND-ROM. Thus, there are no grounded capacitors to generate a false voltage drop (V BL-CS ) on a precharged BL due to charge sharing in the sensing phase.During sensing, only one SL of the selected sector (STR[p]) is discharged to ground, as Fig. 14.6.2 shows. The grounded SL provides the I CELL to discharge the selected BL for reading a 0-cell during the SG pulse (T SG ). A 1-cell, without a metal code-layer shorting its source and drain, is off (WL= 0) during sensing and its BL remains at V DD . The other SL of the selected sectors in the DSSL array is kept at V DD . If the neighboring bitcells (BC[n-1] and BC[n+1]) are 0-cells, this DSSL scheme does not furnish neighboring NDCs with the driving source required to develop their BL voltage drops onto neighboring BLs (BL[n-1] and BL[n+1]) of the selected BL[n] due to dummy read-0 ope...

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mentioning

confidence: 99%

A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications

Chang

Yang

Liang

et al. 2010

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

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“…Its saturation current is the maximum current sink for a ROM cell (0-cell) to discharge the relevant bit line which is pre- Technology Node (um) Cell Size (um ) set to V DD during read access [6], [7]. The value is about 275μA at V DD = 1.8V.…”

Section: Ground Bouncementioning

confidence: 99%

“…3) to be monitored. Ground bounces V ij , where 0 i 255 and 0 j 511, are derived by sequentially activating all 512 word lines with pulse width of 2ns [7] and cycle time of 10ns. For each source node, the maximum value is recorded.…”

Section: Ground Bounce Simulationmentioning

confidence: 99%

“…The sensing margin is ideally equal to a half of the precharged level V DD , but is often made much smaller in order to gain speed performance [6], [7]. For a typical sensing margin of 150mV in which 50mV is reserved to meet the minimum speed requirement [7], the strapping period of m = 128 can easily fail via-2 coding and that of m = 64 via-1 coding. Because we intend to maintain the same instance footprint regardless of which via layer is to be coded by the user, to choose the two strapping periods necessitates the increase of sensing margin.…”

Section: Sensing Marginmentioning

confidence: 99%

“…Table 1 lists all code-via options provided by this compiler, in terms of permissible assignment of the topmost metal layer. We have presented its sensing scheme in [6] and [7]. The focus of this paper is on array assembly and its impacts on the design considerations.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment

Kwai

Chou

Chang

et al.

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06)

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We present a ROM compiler programmable from via 1 to via n -2, where n is the number of metal layers. The layer on which the code via is landed can be selected by the user. With the coding being able to take place as close to the topmost metal as possible, the turnaround time for a revision is shortened. In this paper, we discuss the array assembly scheme and its impacts on the design considerations by the choice of strapping period.

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Energy Efficient Systems Using Resistive Memory Devices

Chang

Chiu

2013

Emerging Memory Technologies

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A Full Code-Patterns Coverage High-Speed Embedded ROM Using Dynamic Virtual Guardian Technique

Cited by 14 publications

References 20 publications

A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications

A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications

FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment

Energy Efficient Systems Using Resistive Memory Devices

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