A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW

Waters, Allen; Moon, Un-Ku

doi:10.1109/asscc.2015.7387508

Cited by 19 publications

(12 citation statements)

References 1 publication

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“…More importantly, the performance of the proposed ADC naturally improves as process technology advances. Ex- Those from [15][16][17] are measurement results of fabricated chips.…”

Section: Resultsmentioning

confidence: 99%

“…Previous synthesis friendly AMS circuit design works [15][16][17][18][19] adopted the digital automatic placement and routing (APR) flow to generate the layouts by turning off the optimizations that are irrelevant, including logic optimization, timing optimization, etc.…”

Section: Synthesis Methodologymentioning

confidence: 99%

“…The majority of the AMS layout design efforts are still handled manually. Recently, some early attempts (including ADCs [15][16][17], phase-locked loop (PLL) [18], filters [19]) have been made to design AMS circuits to be digital-like and reasonably robust to layout effects (e.g. mismatches), so that they can be described in Hardware Description Languages (HDLs) and synthesized using digital layout synthesis tools.…”

Section: Introductionmentioning

confidence: 99%

“…Ultra-low-power and ultra-low-voltage ADCs compatible with CMOS scaling are in increasingly high demand by emerging applications, including internet-of-things (IoT), autonomous wireless sensor networks (WSN), and biomedical implants. While the ADCs presented in [15][16][17] are fully digitally synthesizable, they did not achieve desirable circuit performances (e.g. Walden figure-of-merit (FOM) [20], signal-to-noise and distortion ratio (SNDR)) nor demonstrate scalability.…”

Section: Introductionmentioning

confidence: 99%

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A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology

Sun

et al. 2017

Proceedings of the 54th Annual Design Automation Conference 2017

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Conventional analog/mixed-signal (AMS) circuits design methodology relying heavily on the use of operational amplifiers (opamps) to process signals in voltage-domain (VD) encounters severe difficulties in advanced nanometer-scale CMOS process. We present a novel scaling compatible, synthesis friendly ring voltage-controlled oscillator (VCO) based time-domain (TD) delta-sigma analog-todigital converter (ADC) whose performance improves as technology advances. Decomposed into digital gates (e.g. inverters) and a small set of simple customized cells (e.g. resistors), its layout is fully synthesizable by leveraging digital layout synthesis tools. Post-layout simulation results demonstrate the scaling compatibility of the proposed ADC and a drastic boost to design productivity.

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“…More importantly, the performance of the proposed ADC naturally improves as process technology advances. Ex- Those from [15][16][17] are measurement results of fabricated chips.…”

Section: Resultsmentioning

confidence: 99%

Section: Synthesis Methodologymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology

Sun

et al. 2017

Proceedings of the 54th Annual Design Automation Conference 2017

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“…On the other hands, the performance of analog ICs designed with advanced CMOS process are limited by low intrinsic device gains, large leakage current and low supply voltage. Therefore, digital implementations of analog and mixed signal ICs become more and more attractive [1][2][3][4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits

Yang

Zhao

et al. 2019

Sci. China Inf. Sci.

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This paper proposes a synthesized injection-locked bang-bang phased-locked loop (SILBBPLL) with high digital controlled oscillator (DCO) frequency resolution. The SILBBPLL is expressed with hardware description language and automatically placed & routed (APR) by using standard digital circuit design flow. As the mismatch issues of the circuits are not considered carefully during the APR design flow, the phase noise performance is severely deteriorated. We adopt pulse injection locking technique to improve the phase noise performance. The DCO frequency resolution is critical for reducing the reference spur in a digital injection-locked PLL. Therefore, we propose novel frequency tuning circuits to increase the DCO frequency resolution so that the reference spurs are reduced. The frequency tuning circuits consist of a standard cell based high-linearity output feedback DAC (OFDAC) and two custom varactors. The OFDAC is used to tune the frequency of the DCO with the custom varactor precisely. The custom varactor is firstly designed, added into the standard cell library, and APR with the standard cells. The SILBBPLL chip with a core area of 0.008 mm 2 is implemented in 65 nm CMOS process. When operating at 1.8 GHz, the measured results show that the root-mean-square (RMS) jitter integrated from 10 kHz to 100 MHz is 1.1 ps, and the power consumption is 1.5 mW with a 0.8-V supply. The proposed SILBBPLL achieves a figure-of-merit (FoM) of −237.4 dB and a reference spur of −50.9 dBc. Keywords synthesized all-digital phased-locked loops (ADPLL), bang-bang phased-locked loop (BBPLL), automatically placed & routed (APR), output feedback DAC (OFDAC), injection-locked Citation Yang J C, Zhang Z, Qi N, et al. A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits.

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Challenges and opportunities toward fully automated analog layout design

et al. 2020

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Realizing the layouts of analog/mixed-signal (AMS) integrated circuits (ICs) is a complicated task due to the high design flexibility and sensitive circuit performance. Compared with the advancements of digital IC layout automation, analog IC layout design is still heavily manual, which leads to a more time-consuming and error-prone process. In recent years, significant progress has been made in automated analog layout design with emerging of several open-source frameworks. This paper firstly reviews the existing state-of-the art AMS layout synthesis frameworks with focus on the different approaches and their individual challenges. We then present recent research trends and opportunities in the field. Finally, we summaries the paper with open questions and future directions for fully-automating the analog IC layout.

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A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW

Cited by 19 publications

References 1 publication

A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology

A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits

Challenges and opportunities toward fully automated analog layout design

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