A fully differential sample-and-hold circuit for high-speed applications

Nicollini, G.; Confalonieri, P.; Senderowicz, D.

doi:10.1109/jssc.1989.572640

Cited by 62 publications

(12 citation statements)

References 4 publications

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“…The current work has the highest input swing with respect to the power supply and the lowest output offset. Its power consumption is high with respect to [3] only. But the THD in [3] is not available, thus comparison cannot be complete.…”

Section: Rsha Performancementioning

confidence: 99%

“…Few SHAs capable of holding the output for a full clock cycle were proposed in the literature [2][3][4][5][6]. A true SHA samples the analog input signal during a short time and then holds the signal during almost the full clock period giving the analog-to-digital converter about twice the time to perform the conversion similar to track-and-hold amplifier (THA).…”

Section: Introductionmentioning

confidence: 99%

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A programmable full clock rectifier and sample-and-hold amplifier for biomedical applications

Harb

2010

Analog Integr Circ Sig Process

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Post-layout Monte Carlo analysis and characterization as function of temperature, process, and mismatch variations of a rail-to-rail full clock fully programmable differential rectifier and sample-and-hold amplifier (RSHA) for biomedical applications are presented in this paper. The RSHA is based on a class AB fully differential two-stage operational amplifier. It uses the Miller compensation capacitor to hold the output and a duplicate of the output stage to ensure proper offset cancellation and common-mode control. The circuit is designed and implemented using a 0.35 lm CMOS technology. Results show that the total harmonic distortion, for an almost rail-to-rail input swing at 10 kHz and at 100 kS/s is equivalent to more than 9 bits in worst case. The dc output offset is below 140 lV and the error introduced by the rectification with respect to the non rectified signal is less than -100 dB. The power consumption is 3 mW with ±1.25 V supplies. The RSHA provides an output valid for more than 85% of the clock cycle.

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Section: Rsha Performancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A programmable full clock rectifier and sample-and-hold amplifier for biomedical applications

Harb

2010

Analog Integr Circ Sig Process

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“…A single-ended S/H circuit in which the output in the sample mode stays in the vicinity of its last hold level is presented in [119]. In [120] the idea is developed rather further by extending the length of the hold phase to the whole clock period. The fully differential circuit was later employed in [98] (the design is also reported in [121]).…”

Section: S/h Circuit Without a Reset Phasementioning

confidence: 99%

“…The fully differential circuit was later employed in [98] (the design is also reported in [121]). The circuit from reference [120] is shown in Figure 5.10. For the sake of clarity the capacitors and switches of only one half circuit are drawn.…”

Section: S/h Circuit Without a Reset Phasementioning

confidence: 99%

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Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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