A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio $\Sigma\Delta$ ADC

Abstract

This paper proposes a fully-digital BIST architecture for the dynamic test of Σ∆ ADCs. The proposed BIST relies on generating a ternary stream that encodes a high-linearity analog sinusoidal and injecting it directly at the input of the Σ∆ modulator. Compared to the well-known bitstream, the use of three logic levels in the ternary stream reduces the quantization noise and, thereby, results in a test with a higher dynamic range that covers the full scale of the ADC. The output response is analyzed on-chip using a simplified version of the sine-wave fitting algorithm to compute the SNDR. A standard SPI bus provides digital external access to the embedded test instruments. The proposed BIST wrapper has been integrated into a 40 nm CMOS 18-bit stereo audio Σ∆ ADC IP core provided by ST Microelectronics. It incurs an overall area overhead of 7.1% and the total test time is 28ms per channel. Experimental results on fabricated chips demonstrate an excellent correlation between the BIST and the standard functional specification test.

Digital-to-Analog Hardware Trojan Attacks

“…The requirement for a high-resolution test stimulus can be relaxed by using non-linear stimulus generators combined with advanced post-processing techniques of the converter's output [44]. Traditional BIST schemes for dynamic testing, i.e., Signal-to-Noise Ratio (SNR), use test stimulus generation performed by sinusoidal signal generators [45], [46] or Σ∆ bitsteams encoding sinusoidal signals [47], and test response analyzers that perform spectral analysis [48] or sine-wave fitting analysis [47].…”

Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs

“…For instance, if an onchip ramp generator could be shared for the test of the column read-out ADCs in a consumer CMOS imager sensor, the area overhead could be below 0.1% of the total system area. In future applications, this system level approach may also allow a complete ADC characterization combining on-chip static and dynamic tests in the same VLSI system by integrating also dynamic stimulus generators, such as the one presented in [40] for Σ∆ ADCs. In this line, the target application defines the type of tests required for the ADCs in the system.…”

Reduced-Code Static Linearity Test of Split-Capacitor SAR ADCs Using an Embedded Incremental <inline-formula> <tex-math notation="LaTeX">$\Sigma\Delta$ </tex-math> </inline-formula> Converter

“…On the other hand, oversampling Σ∆ ADCs are more prone to gain and offset errors, and it has been proved that the incremental Σ∆ modulation is inherently more robust to complex non-linear effects such as idle tone generation and dead zones [19]. In addition, well-known digital test solutions for Σ∆ modulators can be adapted for assuring the correct functionality of the added test circuitry [20], [21]. In the remainder of this section, the basic operation of an IΣ∆ ADC is explained and the design trade-offs for sizing the proposed circuitry are explored.…”