A Fully Integrated 48-GHz Low-Noise PLL with a Constant Loop Bandwidth

Peters, Frank; Glisic, Srdjan; Osmany, Sabbir A.; Scheytt, J. Christoph; Schmalz, K.; Winkler, Wolfgang; Engels, M.

doi:10.1109/smic.2008.27

Cited by 11 publications

(1 citation statement)

References 11 publications

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“…The second technique is shown in Fig. 2 and described in detail in [14] and [15]. It utilizes two feedback paths to the VCO and thus creates a dual-loop structure.…”

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confidence: 99%

An Ultra-Wideband Fast Frequency Ramp Synthesizer at 60 GHz With Low Noise Using a New Loop Gain Compensation Technique

Delden

Pohl

Musch

2018

IEEE Trans. Microwave Theory Techn.

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Phase-locked loops (PLLs) for ultra-wideband, low noise, and linear frequency ramp synthesis exhibit a wide variation of the loop gain, if no compensation method is applied. This impairs the performance of the PLL and the corresponding microwave measurement systems. To overcome the disadvantages of existing compensation techniques, we present a new compensation method based on a phase-frequency detector gain modulation. This offers low hardware complexity and avoids additional noise. Furthermore, we present an ultra-wideband, low noise monolithic microwave-integrated circuit for 60-GHz PLLs. Based on this, a 60-GHz frequency synthesizer with a modulation bandwidth of 22 GHz and a jitter of less than 79 fs at the center frequency are realized. The new compensation technique reduces the variation of the loop gain from 14.2:1 to 1.67:1 and is compared with an existing compensation technique utilizing a voltage-dependent damping network, which reduces the variation of the loop gain to 1.78:1. Due to the reduction of the variation of the loop gain, the maximum ramp slope increases from 22 GHz/2.9 ms up to 22 GHz/0.35 ms. In addition, the time jitter of the output signal of the PLL decreases by up to 18%. Furthermore, the PLL performance is constant in the temperature range from 0 • C to 70 • C.

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“…The second technique is shown in Fig. 2 and described in detail in [14] and [15]. It utilizes two feedback paths to the VCO and thus creates a dual-loop structure.…”

mentioning

confidence: 99%

An Ultra-Wideband Fast Frequency Ramp Synthesizer at 60 GHz With Low Noise Using a New Loop Gain Compensation Technique

Delden

Pohl

Musch

2018

IEEE Trans. Microwave Theory Techn.

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An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

Peters

Osmany

et al. 2010

Analog Integr Circ Sig Process

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We present an integrated fractional-N lownoise frequency synthesizer for satellite applications. By using two integrated VCOs and combining digital and analog tuning techniques, a PLL lock range from 8 to 12 GHz is achieved. Due to a small VCO fine tuning gain and optimized charge pump output biasing, the phase noise is low and almost constant over the tuning range. All 16 sub-bands show a tuning range above 900 MHz each, allowing temperature compensation without sub-band switching. This makes the synthesizer robust against variations of the device parameters with process, supply voltage, temperature and aging. The measured phase noise is -87 dBc/Hz and -106 dBc/Hz at 10 kHz and 1 MHz offset, respectively. In integer-N mode, phase noise values down to -98 dBc/Hz at 10 kHz and -111 dBc/Hz at 1 MHz offset, respectively, were measured.

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An integrated differential 60 GHz sliding-IF receiver in SiGe BiCMOS

Sun

Schmalz

Glisic

et al. 2011

2011 3rd International Conference on Computer Research and Development

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This paper presents an integrated 60 GHz sliding-IF receiver fabricated in a 0.25 ȝm SiGe BiCMOS technology. The receiver chain consists of a front-end and an IF IQ demodulator centered at around 12 GHz. A 48 GHz PLL is used to generate the front-end LO signal and the IF quadrature LO signals. The measured LNA noise figure is around 6.6 dB. Digital words are used to control the VGA gains and IQ mismatches through a Serial Peripheral Interface (SPI) to reduce the number of bond pads. The receiver chip has been mounted onto an application board, where an on-board Vivaldi antenna has already been fabricated. An overall conversion gain of 81 dB has been measured with tuning range larger than 30 dB. In a real in-door environment, error-free transmission with a data-rate of 3.6 Gbit/s has been observed over 15 meters.

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A Fully Integrated 48-GHz Low-Noise PLL with a Constant Loop Bandwidth

Cited by 11 publications

References 11 publications

An Ultra-Wideband Fast Frequency Ramp Synthesizer at 60 GHz With Low Noise Using a New Loop Gain Compensation Technique

An Ultra-Wideband Fast Frequency Ramp Synthesizer at 60 GHz With Low Noise Using a New Loop Gain Compensation Technique

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

An integrated differential 60 GHz sliding-IF receiver in SiGe BiCMOS

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