A fully integrated 77GHz FMCW radar system in 65nm CMOS

Li, Yi-An; Hung, Mei-Chuan; Huang, Shih-Jou; Lee, Jri

doi:10.1109/isscc.2010.5433951

Cited by 64 publications

(19 citation statements)

References 3 publications

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“…For low-power CMOS integration on silicon, the ongoing adaptation of sub-90nm RF-CMOS back-end solutions for vehicular radar at 77 GHz will be a critical starting point as it will provide a complete technology base with on-chip antennas as well as compact transceivers that can reach massmarkets [13]. Encouraged by recent demonstration of a 410 GHz oscillator based on 90nm CMOS devices [14] and empowered by ongoing device scaling, RF-CMOS circuitry will play a central role in the ultra low power integration up to 600GHz [15].…”

Section: Trends Of Wireless Transceiversmentioning

confidence: 99%

“…Also, the dominant applications in the 1 THz range have been medical and security imaging technologies that can do without on-chip integration. However, thanks to the vehicular anti-collision radar and multi-media driven indoor wireless network applications in the 60-90 GHz range, onchip antenna solutions have recently gained momentum [13]. Thus, while much less developed compared to other pieces of the WiNoC puzzle, compact on-chip antenna solutions also appear to be within the reach of silicon mm-wave integration as will be discussed in more detail below.…”

Section: Antenna Considerationsmentioning

confidence: 99%

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Energy-efficient adaptive wireless NoCs architecture

DiTomaso

Kodi

Matolak

et al. 2013

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)

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Abstract-With the increasing number of cores in chip multiprocessors, the design of an efficient communication fabric is essential to satisfy the bandwidth and energy requirements of multi-core systems. Scalable Network-on-Chip (NoC) designs are quickly becoming the standard communication framework to replace bus-based networks. However, the conventional metallic interconnects for inter-core communication consume excess energy and lower throughput which are major bottlenecks in NoC architectures. On-chip wireless interconnects can alleviate the power and bandwidth problems of traditional metallic NoCs. In this paper, we propose an adaptable wireless Network-on-Chip architecture (A-WiNoC) that uses adaptable and energy efficient wireless transceivers to improve network power and throughput by adapting channels according to traffic patterns. Our adaptable algorithm uses link utilization statistics to re-allocate wireless channels and a token sharing scheme to fully utilize the wireless bandwidth efficiently. We compare our proposed A-WiNoC to both wireless/electrical topologies with results showing a throughput improvement of 65%, a speedup between 1.4-2.6X on real benchmarks, and an energy savings of 25-35%.

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Section: Trends Of Wireless Transceiversmentioning

confidence: 99%

Section: Antenna Considerationsmentioning

confidence: 99%

Energy-efficient adaptive wireless NoCs architecture

DiTomaso

Kodi

Matolak

et al. 2013

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)

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“…Figure 9.5.4(c) illustrates a photo of the assembly. The LNA, PA, and RF mixer designs are based on our previous work in 60 and 77GHz [2,4]. The 3-stage LNA achieves gain of 18.5dB, and the 5-stage PA 13dB gain and 6dBm P 1dB .…”

mentioning

confidence: 99%

“…As a result, the two limiters sharpen the sinusoids as square functions, and send them to an edge-triggered flip-flop. The error polarity is therefore applied to (V/I) 2 , which provides pumping current I CP2 (=5I CP1 ) to adjust the VCO control voltage accordingly. Note that to minimize undesired disturbance on the control line, the FD loop must be disabled when the loop is locked.…”

mentioning

confidence: 99%

“…It incorporates a cross-coupled LC oscillator with thick-oxide varactors, which is followed by two stages of tuned amplifiers (M 3 -M 5 ) as buffers. A direct injection-locked frequency divider is employed here as the 1st divider stage, where the injection signal is ac-coupled to the gate of the switch M 7 [2]. Simulation shows that its lock range is approximately equal to 4GHz when V b = 0.8V.…”

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confidence: 99%

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An 87GHz QPSK transceiver with costas-loop carrier recovery in 65nm CMOS

Huang

Yeh

Wang

et al. 2011

2011 IEEE International Solid-State Circuits Conference

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Modern high-speed wireless data links such as 60GHz RF and point-to-point communications activate research on Gb/s transceivers for V-band (50 to 75GHz) and W-band (75 to 110GHz). Conventional approaches in SiGe or III-V compounds simply consume too much power and occupy too large area, in addition to the integration difficulty. In CMOS realizations, baseband processors and high-speed digitizers also increase design complexity and power consumption. This paper introduces a fully integrated CMOS QPSK transceiver with baseband-less carrier-and data-recovery circuitry, significantly reducing power consumption while achieving up to 3.5Gb/s data rate.The QPSK transmitter is shown in Fig. 9.5.1. Providing a prototype for the 81-to-86GHz band and 94GHz band, we set up the carrier at 87GHz. An integer-N frequency synthesizer provides 77.3GHz LO and 9.7GHz IF signals, forming an 8/9-1/9 up-convert architecture. It contains a VCO running at 77.3GHz, ÷8 and ÷16 circuits, a type-IV PFD, a V-to-I converter, and an on-chip 2nd-order loop filter. The frequency arrangement is also applied to the RX, making no potential frequency offset between the two. A QPSK modulator generates 4 phases (0°, 90°, 180°, and 270°) of the 9.7GHz IF signal and sends them to the up-convert mixer, creating the 87GHz RF signal. A mm-Wave balun converts differential RF inputs into single-ended mode to drive the PA. With the input capacitance of M 1 and M 2 absorbed by the mixer's resonance network, the balun achieves conversion loss of 1.4dB if the transformer coupling factor is 0.6. The PA's output is fed into a matched microstrip line, which connects to the waveguide adapter.To perform coherent demodulation, the LO clock in the RX must be synchronized in phase and frequency. Unlike typical baseband approaches that require highspeed ADCs (several GS/s) and signal processors (>1GHz), we realize the carrier recovery in the analog domain (i.e., Costas loop). As depicted in Fig. 9.5.2, the receiver is composed of an LNA, a down-convert mixer, an IF amplifier, a 77.3GHz clock source (VCO) and its ÷8 descendants (9.7GHz I/Q signals), and a phase detector (PD) and a frequency detector (FD) for carrier recovery. After LNA amplification, the incoming RF signal is downconverted into IF by the VCO's clock. Assuming the signal at node A is given bywhere D I , D Q denote the embedded data, ω IF is the LO 2 frequency (=2π×9.7GHz), and Δφ is the phase error between IF and LO 2 . After mixing and limiting, the two outputs V D (t) and V E (t) become D I (t) and D Q (t), respectively, given that −45°<Δφ<45°. The V C (V B ) and V D (V E ) are further mixed together, creating the final output V F proportional to sin(Δφ). As a result, the (V/I) 1 's output I CP1 presents a sinusoidal characteristic as shown in the upper-left corner of Fig. 9.5.2. Denoting pumping current as I P when Δφ = π/4, the PD [together with (V/I) 1 ] gain is given by √2I P . The approximately linear behavior in the vicinity of the origin makes itself a linear PLL with two correlated phase-adjusting...

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A compact W‐band mixer‐first receiver in 65 nm CMOS

Nam

Park

2019

Micro & Optical Tech Letters

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We present a compact W‐band mixer‐first receiver consisting of a passive single‐balanced mixer, on‐chip balun, and a variable gain amplifier with 1.9 GHz of bandwidth over a gain range of 36 dB in 65 nm CMOS. The W‐band front‐end has been implemented aiming at a compact frequency‐modulated continuous‐wave (FMCW) radar as a proximity sensor, and a down‐converting chain for a total power radiometer combined with external low noise amplifier. The measured gain of the W‐band receiver is 25 dB, and the receiver achieves 2.57 dBm of IIP3. The integrated receiver consumes 14.56 mA from a supply voltage of 1.2 V, and the core chip occupies only 0.39 mm2.

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A fully integrated 77GHz FMCW radar system in 65nm CMOS

Cited by 64 publications

References 3 publications

Energy-efficient adaptive wireless NoCs architecture

Energy-efficient adaptive wireless NoCs architecture

An 87GHz QPSK transceiver with costas-loop carrier recovery in 65nm CMOS

A compact W‐band mixer‐first receiver in 65 nm CMOS

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