A fully integrated CMOS frequency synthesizer for Bluetooth

Theil, D.; Durdodt, C.; Hanke, A.; Heinen, Stefan; Waasen, S. van; Seippel, D.; Pham-Stabner, D.; Schumacher, K.

doi:10.1109/rfic.2001.935652

Cited by 30 publications

(6 citation statements)

References 2 publications

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“…The phase noise at 1.0-kHz offset is 124 dBc/Hz. It is worthwhile to mention that the frequency synthesizer designed in 0.25-m CMOS in [3] failed to work beyond 2.41 GHz due to limitations of the conventional prescaler.…”

Section: Resultsmentioning

confidence: 99%

A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier

Shu

Sánchez-Sinencio

Silva-Martínez

et al. 2003

IEEE J. Solid-State Circuits

143

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The design of a 2.4-GHz fully integrated 61 fractional-frequency synthesizer in 0.35-m CMOS process is presented. The design focuses on the prescaler and the loop filter, which are often the speed and the integration bottlenecks of the phase-locked loop (PLL), respectively. A 1.5-V 3-mW inherently glitch-free phase-switching prescaler is proposed. It is based on eight lower frequency 45 -spaced phases and a reversed phase-switching sequence. The large integrating capacitor in the loop filter was integrated on chip via a simple capacitance multiplier that saves silicon area, consumes only 0.2 mW, and introduces negligible noise. The synthesizer has a 9.4% frequency tuning range from 2.23 to 2.45 GHz. It dissipates 16 mW and takes an active area of 0.35 mm 2 excluding the 0.5-mm 2 digital 61 modulator. Index Terms-Capacitance multiplier, CMOS, fractional-, frequency synthesizer, loop filter, phase-switching prescaler, phase-locked loop (PLL), sigma-delta (61). worked on IC design in Zhuhai, China. In the summer and fall of 2000, he worked on PLL design as a Co-op Student at Texas Instruments Incorporated, Dallas, TX. His research interests include analog/RF and mixed-signal circuits design.

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Section: Resultsmentioning

confidence: 99%

A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier

Shu

Sánchez-Sinencio

Silva-Martínez

et al. 2003

IEEE J. Solid-State Circuits

143

View full text Add to dashboard Cite

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“…(4) with N as the divider ratio and Kl,,p = lcp Kvco being the product of the charge pump current and the VCO gain. Setting the derivative of the phase margin to zero, dfo 3 1 1…”

Section: A Common Loop Design Methodsmentioning

confidence: 99%

“…A tradeoff between noise and stability requirements has to be found. Two-point modulation is a efficient technique to compensate the low-pass characteristic of the loop [3], [4]. From the PLL point of view, the greatest problem with an integrated PA is that supply power pushing occurs that changes the VCO tuning voltage.…”

Section: Introductionmentioning

confidence: 99%

Novel Optimization Criteria for Loop Filter Design of Type II PLLs

Erkens

Sappok

Neyer

et al. 2007

2007 IEEE Radio and Wireless Symposium

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The dynamics of phase locked loops (PLLs) are heavily influenced by the right choice of the loop filter parameters. A new approach for determining these parameters to meet the specification of telecommunications standards optimally is presented in this paper. The most common optimization criterium is to minimize the integral error over time of the step response. In a telecommunications system, it is more important to keep the instantaneous frequency error within a specified tolerance bandwidth around a desired frequency. When the power amplifier is integrated with the transceiver circuitry, specifications are even harder to meet. For this reason, an optimization method has been developed that features short settling times with inherent stability for any chosen loop bandwidth.

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“…This makes several flip-flops at the input stage operate at a full speed (i.e. the VCO's output), giving rise to high power consumption [4]. The asynchronous prescaler is based on the phase-switching technique.…”

Section: Introductionmentioning

confidence: 99%

“Time borrowing” technique for design of low-power high-speed multi-modulus prescaler in frequency synthesizer

Yuan

Yang

Dong

et al. 2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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A low power continuous phase-switching multimodulus prescaler is proposed, based on a so called "time borrowing" method. This novel phase-switching control strategy significantly reduces the delay of the phase-switching control loop so the multi-modulus prescaler can work with higher input frequencies and obtain the maximum modulus for a lower power supply. According to the measurement results, such a multi-modulus prescaler fabricated in a 0.35µm CMOS process divides the 2.4GHz input frequency by 48 up to 64 for a minimum power supply voltage of 2.5V. Its maximum power dissipation is only 4.85mW. Compared with some other CMOS multi-modulus prescalers reported lately, our design has demonstrated a considerable improvement in terms of the power-to-speed ratio.

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A fully integrated CMOS frequency synthesizer for Bluetooth

Cited by 30 publications

References 2 publications

A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier

A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier

Novel Optimization Criteria for Loop Filter Design of Type II PLLs

“Time borrowing” technique for design of low-power high-speed multi-modulus prescaler in frequency synthesizer

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