A fully-integrated method for RTN parameter extraction

Abstract

A method for on-chip extraction of random telegraph noise (RTN) parameters from transistors is proposed. Exploiting the nature of exponential distributed RTN events, the proposed circuit enables the automatic extraction of mean RTN time constants from a large array of small-area transistors. The on-chip data processing provides a simplified measurement infrastructure, reduces the measurement time by parallelization and increased efficiency, reduces the data post-processing effort and extends the measurement frequency band. The methodology is demonstrated in a prototype chip fabricated in a 28nm High-k Metal Gate (HK/MG) CMOS technology. The 1.17 mm 2 chip includes two arrays of 18,144 transistors each, analog circuitry for sensing and digitizing the RTN signals and a digital signal processing block. The experimental results agree with expectations.

A Probability-Based Strong Physical Unclonable Function With Strong Machine Learning Immunity

“…The output bit is detected as a stable or random bit by judging whether there is a current change in the time window. To increase reliability, the current sensing scheme [16] with Beta-Multiplier [17] can be used to suppress voltage variation. The soft dark-bit masking method [18] or designing specific rules in selecting transistors for random or stable bits can help suppress the temperature sensitivity.…”

Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits

“…In this scenario, integrated circuits (IC) with transistor arrays have been proposed for massive device characterization of TZV [16] and aging (BTI/HCI) [17]- [23], to reduce test times significantly. Array-based ICs for RTN characterization have been also developed [24], [25]. Recently, the first array-based IC enabling the characterization of all these effects has been proposed [26], [27].…”