A fully pipelined and parallel hardware architecture for real-time BRISK salient point extraction

Azimi, Ehsan; Behrad, Alireza; Ghaznavi‐Ghoushchi, M. B.; Shanbehzadeh, Jamshid

doi:10.1007/s11554-017-0693-4

Cited by 6 publications

(3 citation statements)

References 34 publications

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“…To make correspondence between image features, a similarity measure between their descriptors is used. Karim et al [19] proposed to combine SURF features with FAST [20] or BRISK [20] descriptors to provide an optimal solution for reliable and efficient feature matching. Since different image features may have similar descriptors, a robust matching algorithm needs to be adopted.…”

Section: Feature Extraction and Matching Algorithmsmentioning

confidence: 99%

Analysis of Different Image Enhancement and Feature Extraction Methods

et al. 2022

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This paper describes an image enhancement method for reliable image feature matching. Image features such as SIFT and SURF have been widely used in various computer vision tasks such as image registration and object recognition. However, the reliable extraction of such features is difficult in poorly illuminated scenes. One promising approach is to apply an image enhancement method before feature extraction, which preserves the original characteristics of the scene. We thus propose to use the Multi-Scale Retinex algorithm, which is aimed to emulate the human visual system and it provides more information of a poorly illuminated scene. We experimentally assessed various combinations of image enhancement (MSR, Gamma correction, Histogram Equalization and Sharpening) and feature extraction methods (SIFT, SURF, ORB, AKAZE) using images of a large variety of scenes, demonstrating that the combination of the Multi-Scale Retinex and SIFT provides the best results in terms of the number of reliable feature matches.

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Section: Feature Extraction and Matching Algorithmsmentioning

confidence: 99%

Analysis of Different Image Enhancement and Feature Extraction Methods

et al. 2022

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“…They also do not provide any results for demonstrating accuracy. Azimi et al [31] proposed a fully pipelined and parallel hardware architecture for the detector part of the BRISK algorithm which is a multiscale FAST [19] algorithm. Since their focus is only on detection, they have not implemented the descriptor part of BRISK.…”

Section: Fpga-based Implementations Of Brisk Descriptormentioning

confidence: 99%

A Fully Pipelined FPGA Architecture for Multiscale BRISK Descriptors With a Novel Hardware-Aware Sampling Pattern

Ghaffari

Capson

2022

IEEE Trans. VLSI Syst.

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Binary descriptors have been shown to be faster than nonbinary descriptors while producing comparable results in image matching applications. In recent years, there have been many attempts to design hardware accelerators for extraction of binary descriptors to achieve higher processing rates. One of the well-known methods is the binary robust invariant scalable key point (BRISK) algorithm, which has shown outstanding results in various applications. In this work, we propose a multiscale fieldprogrammable gate array (FPGA)-based hardware architecture for the BRISK descriptor. In addition, a new image sampling pattern for the BRISK algorithm is described which is shown to be more efficient than the original sampling pattern for hardware implementation. Our new sampling pattern decreases the size of the patches containing the key point to one-quarter of the size of that used in the original BRISK algorithm, which leads to a reduction in FPGA resource utilization while maintaining the accuracy of the image matching application. Our proposed design is fully pipelined and achieves a frame rate of 78 fps on images with full HD resolution.

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“…1. Feature detectors are used to locate points of interest in an image [2] [14]. Feature descriptors encode information about point of interest into numerical values that can be used to differentiate one feature from another.…”

Section: Feature Extractionmentioning

confidence: 99%

Untitled

2021

International Journal of Advanced Research in Computer and Comm

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Visual feature extraction is widely used in many of computer vision algorithms such as object detection, stereo matching, image matching, and Visual SLAM. Real-time implementation of visual feature extraction suffers from long latency, and heavy computation. GPUs are commonly used to accelerate computationally intensive applications, but they are power hungry devices and, they have a fixed level of parallelism. To achieve processing optimization for such computationally intensive applications, FPGA, and ASIC are more efficient. In this work, an efficient and optimized FPGA architecture is designed to accelerate the computation of visual feature extraction. FAST and BRIEF algorithms are used in this system because they are simple and efficient when working with mobile and embedded systems. The system uses different frequency clocks for input pixels streaming and for processing to prevent stall cycles and achieve high speed. Multi pixels are processed per single clock cycle using optimized parallel and pipelined architecture. The proposed architecture is implemented on TERASIC DE2-115 FPGA board and tested with different image sizes and achieved very high throughput. The system can detect features up to 1000 frames per second for grayscale images with the size of 480 ×480 pixels.

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A fully pipelined and parallel hardware architecture for real-time BRISK salient point extraction

Cited by 6 publications

References 34 publications

Analysis of Different Image Enhancement and Feature Extraction Methods

Analysis of Different Image Enhancement and Feature Extraction Methods

A Fully Pipelined FPGA Architecture for Multiscale BRISK Descriptors With a Novel Hardware-Aware Sampling Pattern

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