A fully planarized 6-level-metal CMOS technology for 0.25-0.18 micron foundry manufacturing

Lin, Tony; Chen, C.; Hsu, S.Y.; Tsai, M.J.; Yew, Tri‐Rung; Chou, J.W.; Haung, K.T.; Wu, Jun; Ku, Yao-Ching; Liu, C.C.; Yang, Meng-Chuan; Yeh, Wen Kuan; Huang, Chien-Hung; Lur, W.; Huang, H.S.; Sun, S.W.

doi:10.1109/iedm.1997.650514

“…We assume gate capacitance, now around 1.5-2 fF m, will stay constant; although this would seem to demand too-thin gate oxides, high-dielectrics may allow more aggressive scaling of the effective [29]- [31]. We project diffusion capacitance to stay at about half gate capacitance for legged devices, although trench technologies and/or SOI can reduce this dramatically [32].…”

Section: A Gate Delay Scalingmentioning

confidence: 99%

The future of wires

Ho

¹

,

Mai

²

,

Horowitz

³

2001

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Concern about the performance of wires in scaled technologies has led to research exploring other communication methods. This paper examines wire and gate delays as technologies migrate from 0.18-m to 0.035-m feature sizes to better understand the magnitude of the wiring problem. Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays. This result is good news since these "local" wires dominate chip wiring. Despite this scaling of local wire performance, computer-aided design (CAD) tools must still become more sophisticated in dealing with these wires. Under scaling, the total number of wires grows exponentially, so CAD tools will need to handle an ever-growing percentage of all the wires in order to keep designer workloads constant. Global wires present a more serious problem to designers. These are wires that do not scale in length since they communicate signals across the chip. The delay of these wires will remain constant if repeaters are used, meaning that relative to gate delays, their delays scale upwards. These increased delays for global communication will drive architectures toward modular designs with explicit global latency mechanisms.

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“…Yet the use of high-κ oxide dielectrics would allow aggressive scaling of an effective T ox [8][9] [10]. Finally, although diffusion capacitances were scaled down slower than S, shallow trench isolations (STIs) or simply legged devices can cause C diff to scale faster than S [11]. Silicon-on-insulator (SOI) devices could also reduce the impact of diffusion capacitance drastically.…”

Section: Revisiting the Underlying Assumptionsmentioning

confidence: 99%

Interconnect Scaling Implications for CAD

Ho¹,

Mai²,

Kapadia³

et al. 1999

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Interconnect scaling to deep submicron processes presents many challenges to today's CAD flows. A recent analysis by Sylvester and Keutzer examined the behavior of average length wires under scaling, and controversially concluded that current CAD tools are adequate for future module-level designs. In our work, we show that average length wire scaling is sensitive to the technology assumptions, although the change in their behavior is small under all reasonable scaling assumptions. However, examining only average length wires is optimistic, since long wires are the ones that primarily cause CAD tool exceptions. In a module of fixed complexity, under both optimistic and pessimistic scaling assumptions, the number of long wires will increase slowly with scaling. More importantly, as the overall die capacity grows exponentially, the number of modules and thus the total number of wires in a design, will also increase exponentially. Thus, if the design team size and per-designer workload is to remain relatively constant, future CAD tools will need to handle long wires much better than current tools to reduce the percentage of wires that require designer intervention. IntroductionWith process technologies capable of fabricating a billion transistor chip on the horizon, the CAD community faces many new challenges. Notably, interconnect scaling in deep submicron processes may force a fundamental change in current ASIC design methodologies. If interconnect delay becomes a significant fraction of total delay, timing convergence for standard-cell design blocks will become difficult or impossible to achieve with current, crude, fanout-based wire load models. Designers will need new tools and methods to synthesize large blocks in deep submicron technologies.In a 1998 ICCAD tutorial, Sylvester and Keutzer carried out a detailed analysis of interconnect scaling and its potential effects on CAD methodologies [1] [2]. By examining the scaling of average length wires, they concluded that CAD tools are adequate for future module-level designs. We examine the sensitivity of their analysis to a range of possible technology scaling assumptions by modeling their simulations with an RC tree delay model.Since design speeds and timing convergence in synthesis flows are typically constrained by long wires, not averagelength ones, we extend the analysis to long wires. We show that for a fixed complexity design, the number of long wires grows slowly with scaling. If chip complexity remained constant, this increase in long wires could be handled by small improvements in today's CAD design flow. Unfortunately exponentially increasing die capacity exacerbates the increasing number of long wires per module by driving up the number of modules. Thus, with constant design team size, the number of gates per designer will grow exponentially. To prevent the per-designer workload from also growing exponentially the percentage of wires that need manual intervention must fall exponentially. This implies that future tools must handle a greater per...

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“…Yet the use of high-K oxide dielectrics would allow aggressive scaling of an effective Tg^ [8][9] [10]. Finally, although diffusion capacitances were scaled down slower than S, shallow trench isolations (STIs) or simply legged devices can cause Q,jto scale faster than S [11]. Silicon-on-insulator (SOI) devices could also reduce the impact of diffusion capacitance drastically.…”

Section: Revisiting the Underlying Assumptionsmentioning

confidence: 99%

Interconnect scaling implications for CAD

Ho¹,

Mai²,

Kapadia³

et al.

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)

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Interconnect scaling to deep submicron processes presents many challenges to today's CAD flows. A recent analysis by Sylvester and Keutzer examined the behavior of average length wires under scaling, and controversially concluded that current CAD tools are adequate for future module-level designs. In our work, we show that average length wire scaling is sensitive to the technology assumptions, although the change in their behavior is small under all reasonable scaling assumptions. However, examining only average length wires is optimistic, since long wires are the ones that primarily cause CAD tool exceptions. In a module of fixed complexity, under both optimistic and pessimistic scaling assumptions, the number of long wires will increase slowly with scaling. More importantly, as the overall die capacity grows exponentially, the number of modules and thus the total number of wires in a design, will also increase exponentially. Thus, if the design team size and per-designer workload is to remain relatively constant, future CAD tools will need to handle long wires much better than current tools to reduce the percentage of wires that require designer intervention. IntroductionWith process technologies capable of fabricating a billion transistor chip on the horizon, the CAD community faces many new challenges. Notably, interconnect scaling in deep submicron processes may force a fundamental change in current ASIC design methodologies. If interconnect delay becomes a significant fraction of total delay, timing convergence for standard-cell design blocks will become difficult or impossible to achieve with current, crude, fanout-based wire load models. Designers will need new tools and methods to synthesize large blocks in deep submicron technologies.In a 1998 ICCAD tutorial, Sylvester and Keutzer carried out a detailed analysis of interconnect scaling and its potential effects on CAD methodologies [1] [2]. By examining the scaling of average length wires, they concluded that CAD tools are adequate for future module-level designs. We examine the sensitivity of their analysis to a range of possible technology scaling assumptions by modeling their simulations with an RC tree delay model.Since design speeds and timing convergence in synthesis flows are typically constrained by long wires, not averagelength ones, we extend the analysis to long wires. We show that for a fixed complexity design, the number of long wires grows slowly with scaling. If chip complexity remained constant, this increase in long wires could be handled by small improvements in today's CAD design flow. Unfortunately exponentially increasing die capacity exacerbates the increasing number of long wires per module by driving up the number of modules. Thus, with constant design team size, the number of gates per designer will grow exponentially. To prevent the per-designer workload from also growing exponentially the percentage of wires that need manual intervention must fall exponentially. This implies that future tools must handle a greater per...

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A fully planarized 6-level-metal CMOS technology for 0.25-0.18 micron foundry manufacturing

Cited by 5 publications

References 1 publication

The future of wires

The future of wires

Interconnect Scaling Implications for CAD

Interconnect scaling implications for CAD

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