A 0.25 um CMOS technology, with 6 layers of fully planarized interconnect, has been developed for versatile, flexible, and fast turn-around foundry manufacturing. A 0.6 um layout pitch has been successfully demonstrated for active, gate poly, and first metal layers. The 0.25 um, 50 A Tox and the 0.35 um, 65 A Tox devices were designed to support the 2.5 V core and the 3.3 V I/O circuits respectively on the same chip. In addition, high-performance 0.18 um, 40 A Tox transistors are also available for low-power applications at 1.8 V Vcc. Gate-delay is 40 p-sec at 2.5 V for the 0.25 um device, and 35 p-sec at 1.8 V for the 0.18 um device. The embedded 6T SRAM cell size is 6.34 um2. Considerations in process architecture and device design, relevant to foundry manufacturing, are also addressed on this 6-level-metal 0.25 um CMOS technology.

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An advanced 0.25-0.18 um CMOS technology with fully-planarized 6-level-interconnect has been developed for versatile, flexible, and fast turn-around foundry manufacturing. A 0.6 um layout pitch has been successfully demonstrated for active, gate poly, and first metal layers. High performance devices with a dual-oxide (65/50 A) approach were developed for 3.312.5 V I10 and core circuits on the same chip. In addition, 0.18 um, 40 A Tox transistors are also available for low-power applications at 1.8 V Vcc. Gate-delay is 40 p-sec at 2.5 V for the 0.25 um device, and 35 p-sec at 1.8 V for the 0.18 um device. The embedded 6T SRAM cell size is 6.34 um2. Considerations in process architecture and device design for foundry manufacturing are also addressed on this 6-level-metal 0.25-0.18 um CMOS technology.