A Fully Programmable Analog CMOS Rational-Powered Membership Function Generator with Continuously Adjustable High Precision Parameters

Moshfe, Sajjad; Hoseini, Pourya; Khoei, Abdollah; Hadidi, Khayrollah

doi:10.1007/s00034-013-9698-9

Cited by 7 publications

(5 citation statements)

References 10 publications

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“…31 Many programmable MFGs have been reported in the literature. [13][14][15][16][17][18][19] Most of these works have utilized current or transconductance modes to improve design functionality. Kachare et al 13 demonstrated a triangular/trapezoidal MFG in 0.5 μm CMOS technology.…”

Section: Related Workmentioning

confidence: 99%

“…11,12 Various MFGs have been proposed in the literature based on the conventional complementary metal-oxide-semiconductor (CMOS) technology. [13][14][15][16][17][18][19] However, most of them are not capable of working properly in deep nanoscale commercial technologies. Moreover, they cannot fully control the shape of the generated output.…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, analog fuzzifiers with better power savings, fewer transistor counts, smaller chip area, and reasonable speed are more interesting than the other design methods 11,12 . Various MFGs have been proposed in the literature based on the conventional complementary metal‐oxide‐semiconductor (CMOS) technology 13–19 . However, most of them are not capable of working properly in deep nanoscale commercial technologies.…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, the current‐mode and transconductance‐mode MFGs offer more design flexibility, simpler structures, lower energy dissipation, and smaller area 31 . Many programmable MFGs have been reported in the literature 13–19 . Most of these works have utilized current or transconductance modes to improve design functionality.…”

Section: Introductionmentioning

confidence: 99%

“…By employing two s‐shaped and z‐shaped MFG, Khalilzadegan et al proposed a current‐mode triangular/trapezoidal MFG in 0.35 μm standard CMOS process using 36 transistors 14 . Moshfe et al 15 presented a current‐mode analog fuzzifier based on 0.35 μm CMOS technology. This MFG can produce all of the s‐shaped, z‐shaped, triangular, and trapezoidal waveforms using 36 transistors.…”

Section: Introductionmentioning

confidence: 99%

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Ultra‐efficient fully programmable membership function generator based on independent double‐gate FinFET technology

Jooq

Behbahani

Moaiyeri

2023

Circuit Theory & Apps

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SummaryThis paper demonstrates an ultra‐efficient, fully programmable membership function generator (MFG) utilizing independent double‐gate (IDG) FinFET technology. The proposed MFG can produce s‐shaped, z‐shaped, triangular, and trapezoidal membership functions. By employing only six transistors, the designed MFG provides full controllability over the height, position, width, and slope of the generated waveforms. Without using any additional transistor and changing the dimensions, the proposed MFG can calibrate the slope of the output based on the back‐gate bias voltage of the IDG‐FinFETs. According to our extensive simulations, the proposed MFG shows promising improvements in transistor count (70%), power‐delay‐product (PDP) (80%), and maximum absolute error (61%) as compared with its state‐of‐the‐art counterparts. To benchmark the functionality of the proposed MFG in practical applications, our generated membership function is exploited as the neuron's activation function in a multilayer perceptron (MLP) neural network. The simulation results indicate that the training process of the simulated MLP with the proposed MFG closely tracks the results obtained from the ideal MLP with the sigmoid activation function. A figure of merit (FoM) is defined considering the hardware efficiency and accuracy of the neural networks to evaluate the entire performance of the proposed MFG. The FoM simulations demonstrate that the proposed MFG presents an excellent trade‐off between hardware performance and accuracy in neural network applications. Our results emphasize that the proposed MFG is a potential candidate for designing high‐performance on‐chip neural networks.

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