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In this paper, a new CMOS four-quadrant analog multiplier circuit is proposed, based on a pair of dualtranslinear loops. The significant features of the circuit are its high accuracy and high linearity as well as its body effect-free operation, owing to the fact that the circuit relies on a new dual-translinear topology. In addition, harmonic distortions are precisely discussed due to their conceivable mismatches, including transconductance and threshold voltage of the transistors. HSPICE postlayout simulation results are presented to verify the validity of the theoretical analysis, where under a supply voltage of 2.8 V, the bandwidth of the proposed multiplier is 137 MHz, and the corresponding maximum linearity error remains as low as 1.12%. Moreover, the power dissipation of the proposed circuit is found to be 521 µ W. The presented multiplier is expected to be useful in the design of various analog signal processing applications such as modulators and frequency doublers, as illustrated in this paper.

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A new strategy to implement exponential circuit in CMOS technology is presented in this paper. The proposed method is based on the new approximation function optimized by linear least squares approach to extend the output dynamic range. The current mode method is employed for realization of circuits, because of simple circuitry and intuitive topology. Unlike to the some reported circuits which were designed in the subthreshold region, the proposed design operates in the saturation region which provides acceptable bandwidth for the circuit. In order to validate the circuit performance, the post layout simulation results are presented using HSPICE and Cadence with TSMC level 49 (BSIM3v3) parameters for 0.18 μm CMOS technology. The results demonstrate 78 dB output dynamic range with the linearity error less than ±0.5 dB which shows a remarkable improvement in comparison with previously reported works. A bandwidth of 67 MHz, maximum power consumption of 0.326 mW under supply voltage of 1.5 V, and 0.77% error for temperature variations are further achievement of the design.