Design of a new low loss fully CMOS tunable floating active inductor

Momen, Hadi Ghasemzadeh; Yazgi, Metin; Kopru, Ramazan; Saatlo, Ali Naderi

doi:10.1007/s10470-016-0784-3

Cited by 29 publications

(8 citation statements)

References 20 publications

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“…16 2.2 | AIs transistor level implementation 2.2.1 | Basic AI topology As mentioned above, an AI based on gyrator topology can be implemented using positive transconductance and a negative transconductance connected back to back with a loaded capacitor C. For the basic CMOS transistor level implementation, various topologies have been proposed and investigated in literature. [19][20][21][22] The most popular structure is that proposed by Thanachayanont and Payne in 1996. 23 It is known as "Simple Grounded Active Inductor."…”

Section: Theory Analysis Of Aismentioning

confidence: 99%

RF and microwave reconfigurable bandpass filter design using optimized active inductor circuit

Hammadi

Haddad

Saad

et al. 2018

Int J RF Microw Comput Aided Eng

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In this article, a design methodology of an active bandpass filter (BPF) using tunable active inductor (TAI) achieving wide frequency contiguous tuning range (FTR) is presented. The tunable BPF is realized with a differential TAI (DTAI) employing two‐reconfiguration mechanisms one for coarse‐tuning using a controllable current source while the fine‐tuning is performed through a variable feedback resistance. The center frequency tuning is performed through the variation of the DTAI control voltages. A cross‐coupled pair based negative resistance technique is also applied to compensate the resistive losses of equivalent RLC resonator. The filter performances are significantly improved using several optimization techniques such as voltage scaling and multigate finger techniques. The proposed BPF is simulated using 0.13 μm CMOS technology. The filter achieves an insertion loss (IL) of 26.62‐33.45 dB over the tuning range 1.16‐3.27 GHz with a relative bandwidth of 1.3%‐3.4%. The noise figure and input 1‐dB compression point at 1.84 GHz are 14.93 dB and 2.72 dBm, respectively. The designed RF filter consumes an average power of 5 mW at 1 V supply voltage.

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Section: Theory Analysis Of Aismentioning

confidence: 99%

RF and microwave reconfigurable bandpass filter design using optimized active inductor circuit

Hammadi

Haddad

Saad

et al. 2018

Int J RF Microw Comput Aided Eng

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“…Consequently, even rapid advancements in integrated circuit technologies cannot keep the passive inductors in the preferred list of RFIC designers. The concept of the active inductor is a consequence of the gyrator-capacitor model [18][19] as shown in Fig. 2.…”

Section: Introductionmentioning

confidence: 99%

CMOS series-shunt single-pole double-throw transmit/receive switch and low noise amplifier design for internet of things based radio frequency identification devices

Bhuiyan

2020

Informacije MIDEM

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The incompatibility between current radio frequency identification (RFID) standards has led to the need for universal and wireless fidelity (Wi-Fi) compatible RFID for internet of things (IoT) applications. Such a universal RFID requires a single pole double throw (SPDT) switch and a low noise amplifier (LNA) to direct and amplify the received raw signal by the antenna. The SPDT suffers from low isolation, high insertion loss and low power handling capacity whereas the LNA suffers from smaller gain, bulky die area, lesser quality (Q) factor, limited tuning flexibility etc. because of passive inductor usage in current generation of devices. In this research, complementary metal oxide semiconductor (CMOS) based inductorless SPDT and LNA designs are proposed. The SPDT adopts a series-shunt topology along with parallel resonant circuits and resistive body floating in order to achieve improved insertion loss and isolation performance whereas the LNA design is implemented with the gyrator concept in which the frequency selective tank circuit is formed with an active inductor accompanied by the buffer circuits. The post-layout simulation results, utilizing 90 nm CMOS process of cadence virtuoso, exhibit that our SPDT design accomplishes 0.83 dB insertion loss, a 45.3 dB isolation, and a 11.3 dBm power-handling capacity whereas the LNA achieves a peak gain of 33 dB, bandwidth of 30 MHz and NF of 6.6 dB at 2.45 GHz center frequency. Both the SPDT and LNA have very compact layout which are 0.003 mm 2 and 127.7 μm 2 , respectively. Such SPDT and LNA design will boost the widespread adaptation of Wi-Fi-compatible IoT RFID technology.

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“…Active inductors are used in many applications such as Wilkinson power drives, phase shifters, active filters, oscillators, low noise amplifiers and matching networks [1]. There are many existing approaches to design floating inductors [1]- [15]. For example, the design in [1] used the Gyrator approach and the range of the active inductor was 6-284nH.…”

Section: Introductionmentioning

confidence: 99%

“…There are many existing approaches to design floating inductors [1]- [15]. For example, the design in [1] used the Gyrator approach and the range of the active inductor was 6-284nH. In [2], the authors presented a grounded and floating active inductance simulator.…”

Section: Introductionmentioning

confidence: 99%

“…The design in [9] presented a novel floating lossy-inductance realization using two negative impedance converters and three passive elements. The work in [1] presented a floating inductance simulator. The design is based on using the parasitic capacitance of the MOSFETs and the maximum inductance was 300nH, which is suitable for high frequency applications.…”

Section: Introductionmentioning

confidence: 99%

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Realization of a Large Values Floating and Tunable Active Inductor

Al-Absi

2019

IEEE Access

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This paper presents a new design for active inductor (AI) realization in addition to capacitance and resistance multipliers. The design uses one current conveyor (CCII±) and one dual-output transconductance amplifier(DO-OTA) and a grounded capacitor. The functionality of the design is confirmed using experimental verification and simulation. Simulation results show that the realized inductance is tunable be tuned from few mH to 2H and more and the multiplication factor for the resistance multiplier is more than 2200 while the capacitance multiplication factor is around 500. A CMOS version of the AI is designed and simulated using Tanner Tspice in 0.18µm CMOS technology. The simulation results confirm the functionality of the design.INDEX TERMS Tunable active inductance, resistance multiplier, capacitance multiplier, integrated circuits.

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Design of a new low loss fully CMOS tunable floating active inductor

Cited by 29 publications

References 20 publications

RF and microwave reconfigurable bandpass filter design using optimized active inductor circuit

RF and microwave reconfigurable bandpass filter design using optimized active inductor circuit

CMOS series-shunt single-pole double-throw transmit/receive switch and low noise amplifier design for internet of things based radio frequency identification devices

Realization of a Large Values Floating and Tunable Active Inductor

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