A Functional 41-Stage Ring Oscillator Using Scaled FinFET Devices With 25-nm Gate Lengths and 10-nm Fin Widths Applicable for the 45-nm CMOS Node

Collaert, N.; Dixit, Abhisek; Goodwin, M.J.; Anil, K.G.; Rooyackers, R.; Degroote, B.; Leunissen, L. H. A.; Veloso, A.; Jonckheere, R.; Meyer, K. De; Jurczak, M.; Biesemans, S.

doi:10.1109/led.2004.831585

Cited by 41 publications

(24 citation statements)

References 8 publications

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“…Without an internal output buffer, the RO demonstrates spontaneous oscillation centered at ~13.4 MHz and provides near rail-to-rail output swing (OS). Many groups [14][15][16][17] have reported approaches towards improving RO oscillation frequency, but little attention has been paid to the equally important issue of rail-to-rail swing in dynamic behavior. In fact, limited dynamic swings can lead to unmatched input/output ranges among adjacent logic gates and cause circuit malfunction.…”

Section: Resultsmentioning

confidence: 99%

“…ROs require the integration of both n-and p-FETs and have strict, high performance requirements with respect to both types of devices. Indeed, because the performance of a RO is so sensitive towards many important NW metrics, nanowire-or nanotube-based ROs have been widely investigated [6,[14][15][16][17][18]. In general, these published devices exhibit oscillation frequencies in the MHz to >100 MHz range, but other circuit characteristics, such as output swing (which is the oscillation voltage amplitude) have been poor.…”

Section: Introductionmentioning

confidence: 99%

“…SiNW-based devices can be fabricated from both bottom-up (materials grown) NWs [15,16] or topdown, lithographically patterned NWs [6,14]. Our own SiNWs, which are formed using the SNAP method [19,20], are somewhere in between these two limits.…”

Section: Introductionmentioning

confidence: 99%

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High performance ring oscillators from 10-nm wide silicon nanowire field-effect transistors

et al. 2011

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We explore 10-nm wide Si nanowire (SiNW) field-effect transistors (FETs) for logic applications, via the fabrication and testing of SiNW-based ring oscillators. We report on SiNW surface treatments and dielectric annealing, for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio (~10 8 ), low drain-induced barrier lowering (~30 mV) and low subthreshold swing (~80 mV/decade). The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs are also explored. The inverter demonstrates the highest voltage gain (~148) reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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High performance ring oscillators from 10-nm wide silicon nanowire field-effect transistors

et al. 2011

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“…Also, the default contact resisitvity and mobility values are to be fine-tuned to match with that of the actual experimental data. So the calibration of the TCAD tool has been done by matching both the ac and the dc characteristics of fabricated FinFETs [10], [11] with that of the simulated devices. The contact resisitvity value chosen for the simulations is 1.45 × 10 −7 Ω · cm 2 .…”

Section: Tcad Tool Calibrationmentioning

confidence: 99%

Device Design and Optimization Considerations for Bulk FinFETs

Manoj

Nagpal

Varghese

et al. 2008

IEEE Trans. Electron Devices

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Abstract-Fabrication of FinFETs using bulk CMOS instead of silicon on insulator (SOI) technology is of utmost interest as it reduces the process costs. Using well-calibrated device models and 3-D mixed mode simulations, we show that bulk FinFETs can be optimized with identical performances as that of SOI FinFETs. Optimized bulk FinFETs are compared with the corresponding SOI FinFETs for a range of technology nodes using an extensive simulation and design methodology. Further, we extend the concept of body doping in bulk FinFETs to the case of lightly doped fins unlike the heavily doped fin cases reported earlier. The optimum body doping required for bulk FinFETs, and its multiple advantages are also systematically evaluated. We also show that device parasitics play a crucial role in the optimization of nanoscale bulk FinFETs.

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“…We calibrated the parameters such as mobility and contact resistivity by benchmarking our TCAD simulations with a set of experimental data of FinFET devices [5]. To cross check the validity of our TCAD tuning exercise we performed the circuit simulation of a 41 stage ring oscillator [6] using the Look Up Table (LUT) approach [7]. The LUT data was generated from the TCAD tool using the calibrated tuned set of parameters.…”

Section: Simulation Detailsmentioning

confidence: 99%