Device Design and Optimization Considerations for Bulk FinFETs

Manoj, C.R.; Nagpal, M.; Varghese, D.; Rao, V. Ramgopal

doi:10.1109/ted.2007.912996

Cited by 58 publications

(27 citation statements)

References 17 publications

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“…To control short channel effects (SCEs) following doping profiles are studied in our work: Subthreshold slope of profile reported in [14] is 78 mV/Decade and DIBL of device is 46 mV/decade which is a significant improvement over uniform low channel doping as discussed earlier.…”

Section: Non Uniform Channel Doping Of Bulk Finfetmentioning

confidence: 97%

“…As a result the drain and source depletion regions will become smaller and will not establish a parasitic current path. In this section of work, Bulk FinFET with heavy body doping (punch through stopper doping) [14] simulated for optimum value of doping. Since a higher bulk doping increases the subthreshold swing at the same time, this method is not the most efficient one to reduce drain-source leakage.…”

Section: Heavily Doped Bulk Finfetmentioning

confidence: 99%

“…Further, Bulk FinFET of heavy body doping i.e. Punchthrough stopper [14] and Piegate bulk FinFET i.e. isolation oxide with source/drain-tobody (S/D) junctions shallower than gate at bottom [15] is reported as Fig 1. Here, Pie-gate structure (Fig 2) is basically represented by misalignment (ΔX j =negative) between the S/D junctions and the bottom of the gate electrode.…”

Section: Introductionmentioning

confidence: 99%

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Optimization of Pie-gate Bulk FinFET Structure

Tripathi¹,

Vadthiya²,

Mishra³

2012

IJCA

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In this paper we propose a novel Pie gate bulk FinFET structure for logic applications suitable for system-on-chip (SOC) requirements. The influence of gate at bottom to junction depth, misalignment was examined for deeper junctions and shallower junctions. It has shown that bulk FinFET with source/drain to body (S/D) junctions shallower than gate at bottom has equal or better subthreshold performance than SOI FinFET. Further, we extend the concept of heavy body doping in bulk FinFETs of Pie-gate structure. The characteristics of such bulk FinFET structure is analyzed by 3D device simulation and compared with SOI FinFET. General termsBulk Fin-shaped field-effect transistor (FinFET), shortchannel performance, SS, DIBL, sentaurus TCAD device simulator.

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Section: Non Uniform Channel Doping Of Bulk Finfetmentioning

confidence: 97%

Section: Heavily Doped Bulk Finfetmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Optimization of Pie-gate Bulk FinFET Structure

Tripathi¹,

Vadthiya²,

Mishra³

2012

IJCA

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“…The mobility models also include mobility degradation due to scattering and high lateral and perpendicular electric fields. Additional steps to calibrate the Sentaurus tools for a completely accurate simulation of FinFETs are discussed in [26]. The results of simulations are compared with UFDG in Fig.…”

Section: Characteristics Of Low and High-v Th Devicesmentioning

confidence: 99%

Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits

Rostami

Mohanram

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper describes the electrode work-function, oxide thickness, gate-source/drain underlap, and silicon thickness optimization required to realize dual-V th independent-gate FinFETs. Optimum values for these FinFET design parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-V th FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional CMOS gates, e.g., implementing 12 unique Boolean functions using only four transistors. Circuit designs that balance and improve the performance of the novel gates are described. The gates are designed and calibrated using the University of Florida double-gate model into conventional and enhanced technology libraries. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz, the enhanced library reduces total power and the number of fins by 36% and 37%, respectively, over a conventional library designed using shorted-gate FinFETs in 32 nm technology.

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“…3-D MOSFET structures, such as double-gate (DG) and triple-gate (TG) FinFETs, provide not only superior immunity to SCEs, the ideal subthreshold slope, and the higher drive current but also the compatibility with conventional CMOS process technology [2]. Although the research on 3-D transistors has been recently in active progress, most design guidelines for device parameters have been focused on the DC characteristics including SCEs or the drive current [3,4] and the hot carrier reliability [5]. In nanoscale digital VLSI circuits, on the other hand, it is worthwhile to elaborately control both the parasitic capacitance and capacitive coupling between the input and the output in order to estimate the influence on the circuit performance [6].…”

Section: Introductionmentioning

confidence: 99%

Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs

Kim¹,

Jang²,

Yun³

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness (T mask ) to the sidewall oxide thickness (T ox ) is T mask /T ox =10/2 nm for the minimum logic delay (τ) while T mask /T ox =5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length (L G ) and the fin width (W fin ) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized T mask /T ox , the propagation delay (τ) decreases with the increasing fin height H fin . It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as H fin increases. In the end, the sensitivity of Δτ/ΔH fin or ΔI ON '/ΔH fin decreases as L G /W fin is scaled-down.However, W fin should be carefully designed especially in circuits that are strongly influenced by the selfcapacitance or a physical layout because the scaling of W fin is followed by the increase of the selfcapacitance portion in the total load capacitance.

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Device Design and Optimization Considerations for Bulk FinFETs

Cited by 58 publications

References 17 publications

Optimization of Pie-gate Bulk FinFET Structure

Optimization of Pie-gate Bulk FinFET Structure

Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits

Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs

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