A functional MOS transistor featuring gate-level weighted sum and threshold operations

Shibata, Tadashi; Ohmi, Tadahiro

doi:10.1109/16.137325

Cited by 547 publications

(201 citation statements)

References 17 publications

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“…This is reflected as a scattered shape in the graphics representing the simulation results, which is more evident as the gain of the comparator used by the logic style is made larger. In the comparison, two different FGMOS logic styles were used: Floating-Gate Complementary MOS transistor logic (FG-CMOS) [8] and Positive-Feedback Floating-Gate Logic (PFFGL) [9]. Using a single ended and a differential FGMOS logic provides information about the influence of the gate architecture on both, noise margin and short-circuit current.…”

Section: Methodsmentioning

confidence: 99%

Noise margin and short-circuit current in FGMOS logics

Cisneros-Sinencio

Díaz-Sánchez

Ramírez-Angulo

2011

IEICE Electron. Express

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Even when floating-gate logics are very-low-voltage circuits, as power supply is reduced, large fan-in FGMOS gates are prone to fail. Thus, determining the negative impact of noise margin and short-circuit current in this type of circuits is crucial to achieve optimal operation for a particular application. For this reason, a systematic and reliable technique for obtaining the correlation between fan-in and supply voltage, simultaneously considering noise margin and short-circuit current, is proposed.

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Section: Methodsmentioning

confidence: 99%

Noise margin and short-circuit current in FGMOS logics

Cisneros-Sinencio

Díaz-Sánchez

Ramírez-Angulo

2011

IEICE Electron. Express

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“…This capacitance, called floating-gate capacitance, will make it possible to shift the threshold voltage level of the MOS-transistors. The required effective threshold voltage for the gate will thereby change and the shift is controlled by the floating-gate's node charge voltage [1], [3]. A shift in threshold voltage will also change the static current (and power consumption), normally to a higher value, at the same time as the propagation delay of the circuit will be different (normally smaller).…”

Section: Introductionmentioning

confidence: 99%

“…One of the ways to reduce power is to explore new types of circuits in order to find better circuit techniques for energy savings. Floating-gate MOS (FGMOS) is a circuit technique that has been proposed in several previous works as a potentially good technique to reduce power consumption and still maintain a relatively high speed [1], [2], [3]. FGMOS is normally fabricated using a standard CMOS process where an extra floating-gate capacitance is connected to the transistor's gate node.…”

Section: Introductionmentioning

confidence: 99%

Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply

Alfredsson

Aunet

Lecture Notes in Computer Science

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Abstract. To reduce power consumption in electronic designs, new techniques for circuit design must always be considered. Floating-gate MOS (FGMOS) is one of those techniques and has previously shown potentially better performance than standard static CMOS circuits for ultra-low power designs. One reason for this is because FGMOS only requires a few transistors per gate and still retain a large fan-in. Another reason is that CMOS circuits becomes very slow in subthreshold region and are not suitable in many applications while FGMOS can have a shift in threshold voltage to increase speed performance. This paper investigates how the performance of an FGMOS fulladder circuit will compare with two common CMOS full-adder designs. Simulations in a 120 nm process shows that FGMOS can have up to 9 times better EDP performance at 250 mV. The simulations also show that the FGMOS full-adder is 32 times faster and have two orders of magnitude higher power consumption than that for CMOS.

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“…81. H,eccii~ly, n marvelous w i~y of using floating-gate MOS transistors was proposed [9] in which multiple "control gates" ca:pacitively couple into the floating gate, establishing its voltage as a weighted sum of the input voltages via a capacitive divider. The channel of the floating-gste transistor then forms a current which is a nonlinear function of the voltage on the floating gate.…”

Section: Introductionmentioning

confidence: 99%

“…The channel of the floating-gste transistor then forms a current which is a nonlinear function of the voltage on the floating gate. In [9] If any particular iiiput current is less than this saturation current, the drain voltage of the corresponding input transistor will begin to fall, at first reducing the saturation current of all of the transistors in t,hr circuit via t>he capacitive coupling to the floatha gate. F:veiituall~.…”

Section: Introductionmentioning

confidence: 99%

A νMOS soft-maximum current mirror

Minch

Diorio

Hasler

et al.

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems

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In this paper, we describe a novel circuit consisting of N + 1 MOS transistors and a single floating gate which computes n soft maximumof N current inputs and reflects the result in the output transistor. An intuitive description of the operation of the circuit is given. Data from a working two-input version of the circuit is presented and discussed. The circuit features a high output voltage swing and an interesting feedback mechanism which cauees its output impedance to be comparable to that of a normal MOS transistor despite the fact that the output devicc is a floating-gate transistor. I. I N T R O D U C T I O NAnalog VI31 signal processing has come to be the subject of much interest and active research in recent times. [l] In part,icular, the current-mode approach in which q u atities of interest are represented as currents and voltages play only an incidental role in the operation of the circuit has become the focus of much attention.[a] Arnoiig the plethora of nonlinear operations required to prrforin curreiit-mode signal processing, the maximum function stands out, as being particularly useful. A soft-mazimum function is one which follows the largest input aiid changes ovei in a smooth manncr when the magnitude of two or inore inputs becorric comparable. 'The circuit, preseiited in this paper cornputes a soft--maximum of N current inputs and reiiects tlie rrsult in its outpi:t8.

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A functional MOS transistor featuring gate-level weighted sum and threshold operations

Cited by 547 publications

References 17 publications

Noise margin and short-circuit current in FGMOS logics

Noise margin and short-circuit current in FGMOS logics

Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply

A νMOS soft-maximum current mirror

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