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Abstract. This paper discusses some aspects regarding the use of universal linear threshold elements implemented in a standard double-poly CMOS technology, which might be used for neural networks as well as plain, or mixed-signal, analog and digital circuits. The 2-transistor elements can have their threshold adjusted in real time, and thus the basic Boolean function, by changing the voltage on one or more of the inputs. The proposed elements allow for significant reduction in transistor count and number of interconnections. This in combination with a power supply voltage in the range of less than 100 mV up to typically 1.0 V allow for Power-Delay-product improvements typically in the range of hundreds to thousands of times compared to standard implementations in a 0.6 micron CMOS technology. This makes the circuits more similar to biological neurons than most existing CMOS implementations. Circuit examples are explored by theory, SPICE simulations and chip measurements. A way of exploiting inherit fault tolerance is briefly mentioned. Potential improvements on operational speed and chip area of linear threshold elements used for perceptual tasks are shown.

We present some fundamental aspects on how UVprogrammed floating-gate (FGUVMOS) circuits may be simulated using the AIM-Spice or Eldo simulators and the BSIM3v3 model. We introduce ways of implementing FGUVMOS binary logic simpler than previously reported. Reduction in transistor and capacitor count for some simple NAND and NOR gates are from three to two MOSFETs, and four to three capacitors, respectively. We also show some aspects of a reconfigurable two-transistor circuit capable of computing the CARRY' function for a FULL-ADDER using two MOSFETs, which is more than 90 percent reduction in transistor count compared to earlier reported FGU-VMOS circuits.