Novel recharge semi-floating-gate CMOS logic for multiple-valued systems

Berg, Y.; Aunet, Snorre; Minnotahari, O.; Høvin, M.

doi:10.1109/iscas.2003.1206229

Cited by 50 publications

(33 citation statements)

References 5 publications

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“…The once and for all initialization is synonymous with programming. By recharging the FG frequently we avoid problems with any leakage currents and random or undesired disturbance of the floatinggate charges, and it converts the non-volatile floating gates 2 The logic levels are: 1 = 100mv, 0 = 500mv and 1 = 900mv , V dd = 1V to semi floating gates (SFG) [1]. The reset or recharge scheme may be used to overcome some problems associated with the floating-gate circuit design.…”

Section: Recharge Semi-floating Gate Devicesmentioning

confidence: 99%

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Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices

Gundersen

Berg

2007

37th International Symposium on Multiple-Valued Logic (ISMVL'07)

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Section: Recharge Semi-floating Gate Devicesmentioning

confidence: 99%

“…The Recharge Semi-Floating Gate (RSFG) MVLInverter in figure 1 is an essential building block [5]. It is a key element in Multi-Valued Logic [1]. The Clk pulse (+Clk) is given by the recharge frequency, which is twice the frequency of the input signal.…”

Section: Recharge Semi-floating Gate Devicesmentioning

confidence: 99%

Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices

Gundersen

Berg

2007

37th International Symposium on Multiple-Valued Logic (ISMVL'07)

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“…This is a key element in Multi-Valued Logic [6]. A MVL inverter, also called an analog inverter, is an inverter with a negative feedback mechanism, C f [9].…”

Section: B the Recharged Semi-floating Gate (Rsfg) Ternary Invertermentioning

confidence: 99%

“…The once and for all initialization is synonymous with programming. By recharging the FG frequently we avoid problems with any leakage currents and random or undesired disturbance of the floating-gate charges, and we convert the non-volatile floating gates to Semi Floating-Gates (SFG) [6]. The reset or recharged scheme may be used to overcome some problems associated with the floating-gate circuit design.…”

Section: Introductionmentioning

confidence: 99%

A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices

Gundersen

Berg

2006

36th International Symposium on Multiple-Valued Logic (ISMVL'06)

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Abstract-This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with Recharged SemiFloating Gate Devices. By using balanced ternary notation, it possible to take advantage of carry free addition, which is exploited in designing a fast adder cell. The circuit operates at 1 GHz clock frequency. The supply voltage is only 1.0 Volt. The circuit is simulated by using Cadence R Analog Design Environment, with CMOS090 process parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 metal layers. All the capacitors are metal plate capacitors, based on vertical coupling capacitance between stacked metal plates.

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“…The evolution of the pseudo floating amplifier is related to other known electronic circuits such as: non volatile floating gate circuits (NFG) [1][2][3], semi floating gate circuits (SFG) [4,5], and quasi floating gate circuits (QFG) [6][7][8]. In the last two decades, pseudo floating-gate amplifiers (PFGA) have been researched in order to realize many analog and digital electronic circuits, such as multivalued gate (MV) [9], analog to digital converters [10], band pass filters [11][12][13][14], Bulk controlled tunable filters [15], tunable dual-band pass filters [16], filters based on current-starved PFGA [17,18], reconfigurable analogue circuits [19] to implement mixer and extractor [20] and multiplexer/demultiplexer [21].…”

Section: Introductionmentioning

confidence: 99%

Analysis of the Effect of Channel Leakage on Design, Characterization and Modelling of a High Voltage Pseudo-Floating Gate Sensor-Front-End

Marchetti¹,

Berg²,

Azadmehr³

2017

Electronics

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Abstract:In this paper, we analyze the effects of channel leakage on the design, modelling and characterization of a high voltage pseudo-floating gate amplifier (PFGA) used as sensor front-end. Leakages are known as a major challenge in new modern CMOS technologies, which are used to bias the PFGA, and consequently affect the behavior of the amplifier. As high voltages are desired for actuation of many types of resonating sensors, especially in ultrasound applications, PFGA implemented in high voltage and low leakage technologies, such as older CMOS fabrication processes or power MOSFET can be the only option. The challenge with these technologies used to implement the PFGA is that the leakages are very low, which affect the biasing of the floating gate. However, the numerous advantages of this type of amplifier, implemented with modern fabrication processes, such as high flexibility, compactness, low power consumption , etc. encouraged the authors to research about this topic. This work provides analysis of the working principle and the design rules for this amplifier, emphasizing the major differences between PFGA implemented in low leakage and high leakage technologies. Static and dynamic analysis, input offset and non-linearity of the PFGA are the main topics of this article. Three different design approaches are presented in this paper, in order to provide a more general design procedure and offset compensation for any low leakage PFGA. The amplifier has been simulated in AMS-0.35µm CMOS models for supply voltages of 5 V and 10 V. Two prototypes have been realized to verify the validity of the modelling and the simulation results. Both devices have been realized by using discrete components and mounted on a printed circuit board. In this work, MOSFETs are realized by using commercial IC CD4007UB and 2N7000. Measurement results of the first prototype proved that the implementation of a low leakage PFGA is possible after that the input offset of the amplifier has been compensated. Measurement results of the second prototype have been used to characterize the low leakage PFGA, extracting the best performances from this amplifier, realized with less components and providing a more compact device. Finally, design rules have been summarized in order to implement this amplifier, which enjoys compactness and a relative low power dissipation.

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Novel recharge semi-floating-gate CMOS logic for multiple-valued systems

Cited by 50 publications

References 5 publications

Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices

Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices

A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices

Analysis of the Effect of Channel Leakage on Design, Characterization and Modelling of a High Voltage Pseudo-Floating Gate Sensor-Front-End

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