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In this paper we investigate the efficiency of using temporal and spatial hardening techniques in flip-flop design for single event upset (SEU) mitigation at different supply voltages. We present three novel SEU tolerant flip-flop topologies intended for low supply voltage operation. The most SEU tolerant flip-flop among the proposed flip-flop topologies shows ability of achieving maximum SEU cross-section below cm bit (no SEUs detected) at 500 mV supply voltage, cm bit at 250 mV supply voltage, and cm bit at 180 mV supply voltage. When scaling the supply voltage from 1 V down to 500 mV, 250 mV and 180 mV, the proposed flip-flops achieve at least , and (respectively) reduction in energy per transition compared to a Dual Interlocked Storage Cell based flip-flop when operated at a supply voltage of 1 V. The flip-flops have been designed and fabricated in a low-power commercial 90-nm bulk CMOS process and were tested using heavy ions with LET between MeV-cm mg and MeV-cm mg. Index Terms-Complimentary metal-oxide semiconductor (CMOS), flip-flop, low power, low voltage, radiation tolerant, single event transient (SET), single event upset (SEU).

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