A fuzzy RISC processor

Salapura, Valentina

doi:10.1109/91.890338

Cited by 33 publications

(17 citation statements)

References 21 publications

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“…In order to reduce the lack of fuzzy operations, some developments modifying the architecture of standard processors to support fuzzy computation have been carried out [6], [7]. The 68HC12 microcontroller from Motorola [8] and the ST Five microcontroller family from ST Microelectronics [9] are commercially available devices that use these techniques.…”

Section: Hw/sw Implementation Of Fuzzy Controllersmentioning

confidence: 99%

FPGA Implementation of Embedded Fuzzy Controllers for Robotic Applications

Sánchez-Solano

Cabrera

Baturone

et al. 2007

IEEE Trans. Ind. Electron.

122

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Abstract-Fuzzy-logic-based inference techniques provide efficient solutions for control problems in classical and emerging applications. However, the lack of specific design tools and systematic approaches for hardware implementation of complex fuzzy controllers limits the applicability of these techniques in modern microelectronics products. This paper discusses a design strategy that eases the implementation of embedded fuzzy controllers as systems on programmable chips. The development of the controllers is carried out by means of a reconfigurable platform based on field-programmable gate arrays. This platform combines specific hardware to implement fuzzy inference modules with a general-purpose processor, thus allowing the realization of hybrid hardware/software solutions. As happens to the components of the processing system, the specific fuzzy elements are conceived as configurable intellectual property modules in order to accelerate the controller design cycle. The design methodology and tool chain presented in this paper have been applied to the realization of a control system for solving the navigation tasks of an autonomous vehicle.Index Terms-Autonomous vehicles, embedded systems, fieldprogrammable gate arrays (FPGAs), fuzzy control, intellectual property (IP).

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Section: Hw/sw Implementation Of Fuzzy Controllersmentioning

confidence: 99%

FPGA Implementation of Embedded Fuzzy Controllers for Robotic Applications

Sánchez-Solano

Cabrera

Baturone

et al. 2007

IEEE Trans. Ind. Electron.

122

View full text Add to dashboard Cite

show abstract

“…Optimizing both the parallel analog inference units and dedicated digital learning units, the IIE can reduce the processing delay and power consumption of the complex nonlinear neurofuzzy operations and the learning procedure for new parameter updates. Compared with neurofuzzy realization by a general purpose RISC processor [15] or hardwired processing units [16]- [19], only the IIE can obtain flexibility with the compact neurofuzzy functions, while achieving low power consumption and fast processing speed.…”

Section: Analog/digital Mixed-mode System Implementationmentioning

confidence: 99%

“…Last, unlike the previous ASICs, the processors in [15], [31], and [32] are occupied by FS/NN software running on a general purpose DSPs, an RISC processor, respectively. Or a field-programmable gate array was used to implement FS [33].…”

Section: A Chip Implementationmentioning

confidence: 99%

1.2-mW Online Learning Mixed-Mode Intelligent Inference Engine for Low-Power Real-Time Object Recognition Processor

Lee

Yoo

2013

IEEE Trans. VLSI Syst.

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Object recognition is computationally intensive and it is challenging to meet 30-f/s real-time processing demands under sub-watt low-power constraints of mobile platforms even for heterogeneous many-core architecture. In this paper, an intelligent inference engine (IIE) is proposed as a hardware controller for a many-core processor to satisfy the requirements of low-power real-time object recognition. The IIE exploits learning and inference capabilities of the neurofuzzy system by adopting the versatile adaptive neurofuzzy inference system (VANFIS) with the proposed hardware-oriented learning algorithm. Using the programmable VANFIS, the IIE can configure its hardware topology adaptively for different target classifications. Its architecture contains analog/digital mixed-mode neurofuzzy circuits for updating online parameters to increase attention efficiency of object recognition process. It is implemented in 0.13-µm CMOS process and achieves 1.2-mW power consumption with 94% average classification accuracy within 1-µs operation delay. The 0.765-mm 2 IIE achieves 76% attention efficiency and reduces power and processing delay of the 50-mm 2 image processor by up to 37% and 28%, respectively, when 96% recognition accuracy is achieved.

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“…The implementation of Fuzzy Logic Controllers (FLC) in software suffers from speed limitations due to the sequential program execution and the fact that standard processors do not directly support many fuzzy operations (i.e., minimum or maximum). In an effort to reduce the lack of fuzzy operations several modified architectures of standard processors supporting fuzzy computation exist (Costa et al, 1997;Fortuna et al, 2003;Salapura, 2000). Software solutions running on these devices speed up fuzzy computations by at least one order of magnitude over standard processors, but are still not fast enough for some real-time applications.…”

Section: Introductionmentioning

confidence: 99%