1.2-mW Online Learning Mixed-Mode Intelligent Inference Engine for Low-Power Real-Time Object Recognition Processor

Abstract

Object recognition is computationally intensive and it is challenging to meet 30-f/s real-time processing demands under sub-watt low-power constraints of mobile platforms even for heterogeneous many-core architecture. In this paper, an intelligent inference engine (IIE) is proposed as a hardware controller for a many-core processor to satisfy the requirements of low-power real-time object recognition. The IIE exploits learning and inference capabilities of the neurofuzzy system by adopting the versatile adaptive neurofuzzy inference system (VANFIS) with the proposed hardware-oriented learning algorithm. Using the programmable VANFIS, the IIE can configure its hardware topology adaptively for different target classifications. Its architecture contains analog/digital mixed-mode neurofuzzy circuits for updating online parameters to increase attention efficiency of object recognition process. It is implemented in 0.13-µm CMOS process and achieves 1.2-mW power consumption with 94% average classification accuracy within 1-µs operation delay. The 0.765-mm 2 IIE achieves 76% attention efficiency and reduces power and processing delay of the 50-mm 2 image processor by up to 37% and 28%, respectively, when 96% recognition accuracy is achieved.

Analog Gaussian Function Circuit: Architectures, Operating Principles and Applications

“…In most cases, digital or other analog circuits are attached around a partially tunable Gaussian or Gaussian-like function circuit (Figure 28) to improve the tunability of the Gaussian function curve's three characteristics (height, mean value and variance). The extra components include multiplexers (MUX) [11,81] and/or switches [15,[82][83][84][85] and other digital circuitry (mixed-mode architectures [86]) [82][83][84], series of resistors [19,87,88], DACs [22,28,87] or Analog to Digital converters (ADC) [22], multipliers [28,31,33,87] or tunable current mirrors [89,90], OTAs [91][92][93][94] or other amplifiers [12,87], common mode feedback circuits (CMFB) [22,95], squarers [33], exponentiators [87], current-controlled current-conveyor second generation (CCII) circuits [90], minimum value circuits [96] and additional current correlators [97]. Four representative examples are provided in Figures 29-32.…”

“…... Each implementation uses the extra components differently, but the general concept regarding the added extra components is to enhance the operation of a simple Gaussian function core, for example, to provide variance tunability to the circuit. In particular, multiplexers and switches are used to select the appropriate value from multiple parallel outputs in order to achieve the tunability in the variance [11,15,[81][82][83][84][85]. In a similar manner, the series of resistors alter the Gaussian function output by changing the total resistance value [19,87,88].…”

“…Most of them are mixed-mode implementations which took advantage of both analog and digital circuits. The existing categories include controllers [72,74,79,80,85,88], object recognition inference [82][83][84] or neural perception [31] engines or processors [22], function approximators [71,75] and a min-max network [21]. The presented controllers are hardware-friendly implementations based on classic fuzzy control theory, an example is shown in Figure 42.…”

“…Specifically, References [74,79,80] design a Takagi-Sugeno based controller and [72] realize a Type-2 fuzzy controller. The object recognition applications [22,31,[82][83][84] are based on neuro-fuzzy logic, an example is shown in Figure 43. In particular, a fuzzy system pre-processes the input data for the following perceptron (a single NN layer with an activation function).…”