A FVF LDO Regulator With Dual-Summed Miller Frequency Compensation for Wide Load Capacitance Range Applications

Xiao, Tan; Koay, Kuan Chuang; Chong, Sau Siong; Chan, P.K.

doi:10.1109/tcsi.2014.2309902

Cited by 53 publications

(23 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This current is increased to 3 mA when C OUT and V IN are at their maximum values. On the other hand, the structure proposed in this work remains stable for a minimum current of 0.1 mA, regardless of the C OUT and FOM (fs) [18] [14]…”

Section: Resultsmentioning

confidence: 99%

“…A noninverting gain stage is inserted to drive the gate of the pass transistor, enhancing the slew rate (SR) and the open-loop gain. Tan and others [18] additionally use a dual-summed Miller compensation to stabilize the regulator for a minimum load current of 0 mA. However, despite the increase in the open-loop gain, the circuit is only stable for a minimum output current of 3 mA, and the line transient response has a long settling time.…”

Section: Fvf-based Low-dropout Voltage Regulator With Fastmentioning

confidence: 99%

“…However, despite the increase in the open-loop gain, the circuit is only stable for a minimum output current of 3 mA, and the line transient response has a long settling time. Tan and others [18] additionally use a dual-summed Miller compensation to stabilize the regulator for a minimum load current of 0 mA. In [19], a buffered FVF with a triple-path input error amplifier (EA) is used to improve the PSRR.…”

Section: Fvf-based Low-dropout Voltage Regulator With Fastmentioning

confidence: 99%

See 2 more Smart Citations

FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

et al. 2017

View full text Add to dashboard Cite

A new internally compensated low drop‐out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65‐nm CMOS technology. Measurements show load and line regulations of 433.80 μV/mA and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of 1 μs. The total current consumption is 17.88 μA (for a 0.9 V supply voltage).

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Fvf-based Low-dropout Voltage Regulator With Fastmentioning

confidence: 99%

Section: Fvf-based Low-dropout Voltage Regulator With Fastmentioning

confidence: 99%

See 1 more Smart Citation

FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

et al. 2017

View full text Add to dashboard Cite

show abstract

“…The conventional embedded driving stage (CEDS) is shown in Fig. 5.2(a) which has been widely used in [63], [70], [77]. It is apparent that the CEDS has high output impedance…”

Section: 31proposed Transient-assisted Embedded Driving Stage (I)mentioning

confidence: 99%

“…However, when it is pushed towards sub-1V supply in the context of the trend of low-voltage and low-power SoC environment, the LDO regulator will suffer from the performance degradation in terms of speed and stability due to the substantial increase in the power transistor's size to maintain a high current driving capability. This raises the motivation for the investigation and design of an improved low-voltage FVF LDO regulator using the foundation circuits in [75], [77] to achieve fast transient response under low power constraint. The details of the proposed improved regulator will be presented in the following sections.…”

Section: Introductionmentioning

confidence: 99%

Design of low-power PVT-aware circuits for power management applications

Wang¹

View full text Add to dashboard Cite

show abstract

Digitally‐assisted constant‐on‐time dynamic‐biasing technique for bandwidth and slew‐rate enhancement in ultra‐low‐power low‐dropout regulator

Guo

Leung

et al. 2015

Circuit Theory & Apps

View full text Add to dashboard Cite

SUMMARYA digitally-assisted constant-on-time dynamic-biasing (COT-DB) technique has been proposed to enable significant enhancement in dynamic performances, while the average current consumption can be kept to ultralow level. This dynamic-biasing technique has a predefined magnitude and duration on biasing current boost, which is beneficial to estimate power budget in systems with finite energy source. The proposed technique has been applied to a low-dropout regulator (LDO) to demonstrate the effectiveness. Experimental results show that significant improvements in settling times during load-transients and line-transients are as much as 880×, while the current consumption is only 1.02 μA. In fact, for the same dynamic performances, the average current consumption of LDO with COT-DB technique can be as low as 0.39% of the LDO with heavy static biasing. The digitally-assisted implementation of the technique also allows robust augmentation of the technique onto almost all analog systems.

show abstract

A FVF LDO Regulator With Dual-Summed Miller Frequency Compensation for Wide Load Capacitance Range Applications

Cited by 53 publications

References 19 publications

FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

Design of low-power PVT-aware circuits for power management applications

Digitally‐assisted constant‐on‐time dynamic‐biasing technique for bandwidth and slew‐rate enhancement in ultra‐low‐power low‐dropout regulator

Contact Info

Product

Resources

About