A G3 PowerPC/sup TM/ superscalar low-power microprocessor

Kennedy, A.R.; Alexander, M.; Fiene, E.; Lyon, J.; Kuttanna, B.; Patel, Rilesh; Pham, Mydung; Putrino, M.; Croxton, C.; Litch, S.; Burgess, B.

doi:10.1109/cmpcon.1997.584742

Cited by 10 publications

(1 citation statement)

References 3 publications

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“…The most prominent and widely used among them is Pseudo LRU (PLRU). The PLRU is extensively used in the PowerPC series of microprocessors [6]. The PLRU is implemented as a binary tree, whose leaf nodes are the lines in the set, as shown in Fig.…”

Section: Existing Cache Replacement Policiesmentioning

confidence: 99%

H-NMRU: An Efficient Cache Replacement Policy with Low Area

Roy¹

2010

Int J Parallel Prog

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In present multi-core devices, the individual processors do not need to operate at the highest possible frequencies. Instead there is a need to reduce the power, complexity and area of individual processor components like caches. In this paper we propose a low area, high performance cache replacement policy for embedded processors called Hierarchical Non-Most-Recently-Used (H-NMRU). The H-NMRU is a parameterizable policy where we can trade-off performance with area. We extended the Dinero cache simulator with the H-NMRU policy and performed architectural exploration with a set of cellular and multimedia benchmarks. On a 16 way cache, a two level H-NMRU policy where the first and second levels have 8 and 2 branches, respectively, performs as good as the Pseudo-LRU policy with storage area saving of 27%. Compared to true LRU, H-NMRU on a 16 way cache saves huge amount of area (82%) with marginal increase of cache misses (3%). Similar result was also noticed on other cache like structures like branch target buffers. Therefore, the two level H-NMRU cache replacement policy (with associativity/2 and 2 branches on the two levels) is a very attractive option for caches on embedded processors with associativities greater than 4. We present a case-study where it can be used on the L2 cache with substantial gain in performance and area for single and dual core platforms.

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Section: Existing Cache Replacement Policiesmentioning

confidence: 99%