A gate leakage reduction strategy for future CMOS circuits

Drazdziulis, Mindaugas; Larsson-Edefors, Per

doi:10.1109/esscirc.2003.1257136

Cited by 17 publications

(6 citation statements)

References 5 publications

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“…Fig. 2 shows a diagram of gate tunneling currents in a MOSFET, when drain, source and substrate are grounded [5,[15][16][17][18]. It can be seen that direct tunneling currents not only flow between the channel and the gate, but also between the SDE regions and the gate.…”

Section: Gate and Drain Current Measurementsmentioning

confidence: 96%

Stress induced gate–drain leakage current in ultra-thin gate oxide

Petit

Zander

2007

Microelectronics Reliability

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Section: Gate and Drain Current Measurementsmentioning

confidence: 96%

Stress induced gate–drain leakage current in ultra-thin gate oxide

Petit

Zander

2007

Microelectronics Reliability

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“…Since gate leakage is exponentially related to gate voltage, one way to reduce gate leakage is to reduce the voltage on storage node (XT/XB). A reduced power supply (V DD ) lowers the gate voltage on the storage nodes hence reducing the gate tunneling current [5]. But lowering the voltage on the storage nodes causes static noise margin to decrease resulting into an unstable cell.…”

Section: Introductionmentioning

confidence: 99%

A low leakage and SNM free SRAM cell design in deep sub micron CMOS technology

Jain¹,

Agarwal²

2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

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As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has approached the limit when direct tunneling causes gate leakage in both on state and off state of MOSFET transistor operation modes. Also, lower operating voltage will lower the stability of SRAM cell resulting in lower value of static noise margin. In this paper, a novel read '0' static noise margin (SNM) free eight transistors (8T) SRAM cell is proposed that reduces gate leakage power in the zero state, taking into consideration the fact that in ordinary program most of the bits stored in caches are zeros for both the data and instruction streams. Compared to conventional six transistors (6T) SRAM cell, new 8T SRAM cell reduces total leakage by 50.2% in the zero state at low temperature, where gate leakage is dominant. High V T transistors in 8T SRAM cell can be used to further reduce both gate and sub threshold leakage. This new high V T 8T SRAM cell reduces total leakage by 60% in zero state at highest temperature. The 8T SRAM cell is SNM free in read operation for the case when cell stores logic '0'. Interestingly, new cell improves SNM by 2.2 times as compared to conventional 6T SRAM cell in read operation and standby mode for the case when cell stores logic '1'.

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“…Zur Minimierung der Verlustleistung gibt es bei statischen CMOS Schaltungen verschiedenste Ansätze (Henzler et. al., 2005;Drazdziulis et. al., 2003;Roy et.…”

Section: Introductionunclassified

Power-Clock-Gating in adiabatischen Logikschaltungen

et al. 2006

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Abstract. In statischen CMOS-Schaltungen wird Clock-Gating verwendet, um inaktive Schaltungsgruppen abzuschalten und damit dynamische Verluste zu reduzieren. Leckströme gewinnen in den neuen Technologien zunehmend an Bedeutung, und statische Verluste treten auf, die durch Power-Gating reduziert werden. Da adiabatische Logik eine getaktete Versorgungsspannung benutzt, kann hier mittels eines einzigen Switches sowohl ein Clock- als auch ein Power-Gating implementiert werden. Da der Switch auch die Verluste im eingeschalteten Zustand erhöht, muss ein besonderes Augenmerk auf die Auswahl und die Dimensionierung des Switches gelegt werden. Dieser Artikel zeigt die Grundlagen des Power-Clock-Gatings (PCG) in adiabatischer Logik, Betrachtungen zur Auswahl der geeigneten Switchtopologie und Vorschriften für die Dimensionierung des Switches. Des weiteren wird auf die Auswirkungen des PCG auf den Oszillator eingegangen.

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A gate leakage reduction strategy for future CMOS circuits

Cited by 17 publications

References 5 publications

Stress induced gate–drain leakage current in ultra-thin gate oxide

Stress induced gate–drain leakage current in ultra-thin gate oxide

A low leakage and SNM free SRAM cell design in deep sub micron CMOS technology

Power-Clock-Gating in adiabatischen Logikschaltungen

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