Process variations and atomic-level fluctuations increasingly pose challenges to the design and analysis of integrated circuits by introducing variability. Although several approaches have been proposed to deal with the inherent statistical nature of circuit design, we consider them incomplete with two important aspects often being insufficiently addressed: non-Gaussian distributions and highly correlated parameters. To address these points, we propose a fully multivariate and non-Gaussian approach based on an arbitrary model. A subset of the model parameters is treated as a multi-dimensional random variable, which is represented by a combination of generalized lambda distributions and Spearman rank correlation matrices -a very general approach with nearly arbitrary freedom in distribution shapes and parameter correlations. In our application scenarios, we show that such a model is able to fully and accurately capture variability in device compact models and standard cell performance models. Finally, we present adapted analysis methods making use of these models in circuit simulations and in efficient gate level analyses of digital circuits with high accuracy.
I. INTRODUCTIONP ROCESS VARIATIONS and atomic-level fluctuations result in integrated circuit (IC) performance variability. To achieve circuits fulfilling their specifications, such effects have to be taken into account during circuit design and analysis [1].Global variations shift the parameters of all devices per die equally. They have always affected ICs and can be tackled by corner-based analysis approaches that assume the most extreme parameter combinations [2]. However, local variations, causing identically designed devices on the same die and in close proximity to randomly differ, have rapidly gained importance since the 90 nm technology node [2]. In combination, global and local variations lead to correlated device variability. Neglecting local variations, corner-based approaches are not sufficient any more. Instead, new modeling and analysis methods are required to adequately analyze the impact of variability during IC design [2]-[4].In Sec. II, the state of the art to handle variability is reviewed for device compact models and digital circuit design. This survey shows that a variety of methods already exists, but most of them focus on particular tasks and often make A. Lange, Ch. Sohrmann, R. Jancke, and J. Haase are with the Fraunhofer Institute for Integrated Circuits (IIS), Design Automation Division (EAS), 01069 Dresden, Germany (email: [andre.lange, christoph.sohrmann, roland.janke, joachim.haase]@eas.iis.fraunhofer.de).