SOI FinFET nFET-to-pFET Tracking Variability Compact Modeling and Impact on Latch Timing

Abstract

In this paper, nFET-to-pFET (n-to-p) tracking characteristics in 14-nm silicon-on-insulator (SOI) FinFET technology are studied by technology computer-aided design-based statistical modeling. Compared with planar SOI high-k metal gate CMOS technologies, 14-nm SOI FinFET technology shows better n-to-p tracking mainly due to the strong influence of correlated Fin geometrical variation, as well as reduced uncorrelated variation from an innovative work function process. The impact of the n-to-p tracking characteristics on setup and hold (guard time) of latch circuits is evaluated by corner and Monte Carlo simulation using compact models. It is found that the guard time is significantly modulated by slow/fast and fast/slow corners in certain conditions and, therefore should be considered in guard time design.Index Terms-Integrated circuits design, MOSFETs, semiconductor device modeling, variation aware timing. 0018-9383

A Novel General Compact Model Approach for 7-nm Technology Node Circuit Optimization From Device Perspective and Beyond

“…12. We apply the empirical stochastic fluctuations of Lg and Fin width of POR device with Gauss distribution as process fluctuations [25]. Clamp voltage obeys normal distribution with minimal standard deviation basically, that is, clamp voltage which determines ESD level is immune to process fluctuation.…”