A general approach for regularity extraction in datapath circuits

Abstract

Inmajority ojhigh-performance custom ICdesigns, designers tuke advantage of the high degTee of Regularitypresent in circuits to generate eficient layouts in terms area and perfomance aswellas to Teducethe design effort. Inthis paper, we present a general and comprehensive approach to extTact functional regularity for datapath ciTcuits from their behavioralor structural HDL descn.ptions. The fundamental step is the generation ofa large set of templates, where a template as a subcircuit with multiple instances in the ciTcuit. Two novel template generation algorithms aTe presented -one fortemplates with a tree structure, andtheother foraspecial class of multi-output templates, called single-p n.ncipaloutput (single-PO) templates, wheTe all outputs of a template are in thetransitive faninof a particular output. The set of template$ generated is complete under a few simplifying, yet practical, assumptions. This is key to obtaining a desirable couerof theciTcuit using templates. Weshow that excellent cover$ are obtained for van"ous circuits, including ISCAS benchmarks. We also demonstrate that the regularitg extracted for these circuits can be used to understand their under[ging structure. We have successfully used our approach to identify bit slices of very large datapath circuits from general-purpose microprocessors.

A layout-similarity-based approach for detecting phishing pages

“…The generic regularity extraction problem consists of identifying large existing templates with many instances and covering the graph by the identified templates. Note that this problem was addressed in many different research areas such as in CAD circuit design [2,10,11] or graph mining [5]. For our purposes, regularity extraction consists of identifying the templates with the maximum number of vertices that have got at least two separate instances in the true and the phishing DOM-Trees, allowing some structural differences of the trees.…”

“…In order to polynomially bind the complexity of the templates generation phase, as also assumed by [2], we assign for every vertex v ∈ G by a function k : E → 1, . .…”

“…The templates computation step is based on the approach proposed in [2] to identify equivalent trees in a graph. The algorithm starts from the seeds computed in the initialization phase and proceeds comparing the children vertices of each root iteratively, until compatible vertices are found.…”

Mapping Applications to a Coarse Grain Reconfigurable System

“…1.9. This is an iterative procedure, similar to the methods in Cadambi (1999), Chowdhary (1998), Rao (1993. At each round, after computing an approximate solution for the MISs within each subset, out of all templates in Ω, the heuristic approach selects a template T with a maximum value of the objective function, depending on the weights and approximate solutions for the MISs.…”

“…The algorithms in Cadambi (1999), Chowdhary (1998) provide all templates of a CDFG. The complete set of tree templates and single-PO (single principle output) templates are generated in Chowdhary (1998) and all the single-sink templates (possibly multiple outputs) are found by the configuration profiling tool in Cadambi (1999).…”