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This paper presents a new timing driven force directed placement algorithm that meets physical net length constraints as well as constraints on specific pin sets. It is the first force directed placement algorithm that meets precise half perimeter bounding box constraints on critical nets. It builds on the work of Eisenmann et al. [12], adding a new net model that changes the contribution of constrained nets in the quadratic programming problem, during solving for each force generation step. We propose several methods for selecting and constraining critical nets to achieve improved timing. Our work suggests that the force directed method with net constraints is a powerful tool for placement and timing convergence, achieving an average worst negative slack optimization exploitation of 64% and average total negative slack optimization exploitation of 48% results on 16 industry circuits from a 1.5GHz microprocessor.

We show that the FPGA technology mapping problem can be eciently implemented as a mixed integer linear programming (MILP) problem which generates truly optimal mappings. The MILP approach can handle a wide variety of FPGA logic block architectures. We present a compact MILP formulation for logic blocks based o n l o okup tables (LUTs) or multiplexers. We also show that the MILP formulation can be e asily modied to optimize area, delay, or a combination of both. We demonstrate that moderately large benchmark circuits can be mapped i n a r e asonable time using the MILP approach directly. For larger circuits, we propose a technique of partitioning a circuit prior to mapping, which drastically reduces the computation time with little or no loss in optimality.

Inmajority ojhigh-performance custom ICdesigns, designers tuke advantage of the high degTee of Regularitypresent in circuits to generate eficient layouts in terms area and perfomance aswellas to Teducethe design effort. Inthis paper, we present a general and comprehensive approach to extTact functional regularity for datapath ciTcuits from their behavioralor structural HDL descn.ptions. The fundamental step is the generation ofa large set of templates, where a template as a subcircuit with multiple instances in the ciTcuit. Two novel template generation algorithms aTe presented -one fortemplates with a tree structure, andtheother foraspecial class of multi-output templates, called single-p n.ncipaloutput (single-PO) templates, wheTe all outputs of a template are in thetransitive faninof a particular output. The set of template$ generated is complete under a few simplifying, yet practical, assumptions. This is key to obtaining a desirable couerof theciTcuit using templates. Weshow that excellent cover$ are obtained for van"ous circuits, including ISCAS benchmarks. We also demonstrate that the regularitg extracted for these circuits can be used to understand their under[ging structure. We have successfully used our approach to identify bit slices of very large datapath circuits from general-purpose microprocessors.

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