Timing driven force directed placement with physical net constraints

Rajagopal, Karthikeyan; Shaked, Tal; Parasuram, Yegna; Cao, Tung; Chowdhary, Amit; Halpin, Bill

doi:10.1145/640015.640016

Cited by 25 publications

(26 citation statements)

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“…In a recent paper, [12] reported an average T NS (total negative slack, which is a special case of our FOM when the slack threshold is zero) improvement of 47.6% and W NS improvement of 63.6%. Since we have no access to those test circuits in [12], we cannot make direct comparison with those numbers.…”

Section: Timing Driven Placementmentioning

confidence: 64%

“…Table 2 and Table 3 compare the FOM and W NS results from ZW , W L, T S, and T SF. Since we can not compare directly with other timing driven placement algorithms due to the uniqueness of our flow, we report under the improvement columns for T S and T SF in these tables the optimization potential over W L relative to ZW , which is also used in [12]. The optimization potential is defined as the percentage of timing improvement by timing driven placement versus wire length driven placement, compared to an upper bound for such improvement.…”

Section: Timing Driven Placementmentioning

confidence: 99%

“…Since we have no access to those test circuits in [12], we cannot make direct comparison with those numbers. Also, it should be noted that our test circuits are significantly bigger than those used in [12] (the largest circuit in [12] is only 6K, while ours is over 440K).…”

Section: Timing Driven Placementmentioning

confidence: 99%

“…Another popular net-based placement approach is to assign higher net weights to the more timing critical nets [7] [5] [6] [8] [9] [10]. The net weights may be iteratively updated for multiple placement runs [7] [9] [11] [12]. However, in a modern ASIC physical synthesis flow that needs to deal with millions of placeable cells, global placement is usually performed only two or three times for acceptable turn around time.…”

Section: Introductionmentioning

confidence: 99%

“…T NS is a special case of FOM with zero slack target. But [12] did not use the T NS during placement step to guide it. In this paper, we explicitly use FOM metric to guide the placement.…”

Section: Introductionmentioning

confidence: 99%

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Sensitivity guided net weighting for placement-driven synthesis

Ren

Pan

Kung

2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Net weighting is a key technique in large scale timing driven placement, which plays a crucial role for deep submicron physical synthesis and timing closure. A popular way to assign net weight is based on the slack of the nets, trying to minimize the worst negative slack (WNS) for the entire circuit. While WNS is an important optimization metric, another figure of merit (FOM), defined as the total slack difference compared to a certain slack threshold for all timing end points, is of equivalent importance to measure the overall timing closure result for highly complex modern ASIC and microprocessor designs. In this paper, we perform a comprehensive analysis of the slack and FOM sensitivities to the net weight, and propose a new net weighting scheme based on the slack and FOM sensitivities. Such sensitivity analysis implicitly takes potential physical synthesis effect into consideration. Experiment results on a set of industrial circuits are promising for both stand-alone timing driven placement and physical synthesis afterwards.

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Section: Timing Driven Placementmentioning

confidence: 64%

Section: Timing Driven Placementmentioning

confidence: 99%

Section: Timing Driven Placementmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…T NS is a special case of FOM with zero slack target. But [12] did not use the T NS during placement step to guide it. In this paper, we explicitly use FOM metric to guide the placement.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Sensitivity guided net weighting for placement-driven synthesis

Ren

Pan

Kung

2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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An LP-based methodology for improved timing-driven placement

Wang¹,

Lillis²,

Sanyal³

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

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Abstract-A method for timing driven placement is presented. The core of the approach is optimal timing-driven relaxed placement based on a linear programming (LP) formulation. The formulation captures all topological paths in a linear sized LP and thus, heuristic net weights or net budgets are not necessary. Additionally, explicit enumeration of a large number of paths is avoided. The flow begins with a given placement and iteratively extracts timing-critical sub-circuits, optimally places the sub-circuit by LP and applies a timing-driven legalizer. The approach is applied to the FPGA domain and yields an average of 19.6% reduction in clock period of routed MCNC designs versus [6] (with reductions up to 39.5%).

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Timing-driven placement based on monotone cell ordering constraints

Hwang¹,

Pedram²

Asia and South Pacific Conference on Design Automation, 2006.

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Abstract− In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed that most of the paths that cause timing problems in the circuit meander outside the minimum bounding box of the start and end nodes of the path. To limit this undesirable behavior, we impose a physical constraint on the placement problem, i.e., we assign a preferred signal direction to each critical path in the circuit. Starting from an initial placement solution, by using a move-based optimization strategy, these preferred directions force cells to move in a direction that maximizes the monotonic behavior of the timing-critical paths in the new placement solution. To make the direction assignment tractable, we implicitly group all circuit paths into a set of input-output conduits and assign a unique preferred direction to each such conduit. We integrated this idea into a recursive bipartitioning-based placement framework with a min-cut objective function. Experimental results on a set of standard placement benchmarks show that this approach improves the result of a state-of-the-art industrial placement tool for all the benchmark circuits while increasing the wire length by a tolerable amount.

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Timing driven force directed placement with physical net constraints

Cited by 25 publications

References 0 publications

Sensitivity guided net weighting for placement-driven synthesis

Sensitivity guided net weighting for placement-driven synthesis

An LP-based methodology for improved timing-driven placement

Timing-driven placement based on monotone cell ordering constraints

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