Technology mapping for field-programmable gate arrays using integer programming

Abstract

We show that the FPGA technology mapping problem can be eciently implemented as a mixed integer linear programming (MILP) problem which generates truly optimal mappings. The MILP approach can handle a wide variety of FPGA logic block architectures. We present a compact MILP formulation for logic blocks based o n l o okup tables (LUTs) or multiplexers. We also show that the MILP formulation can be e asily modied to optimize area, delay, or a combination of both. We demonstrate that moderately large benchmark circuits can be mapped i n a r e asonable time using the MILP approach directly. For larger circuits, we propose a technique of partitioning a circuit prior to mapping, which drastically reduces the computation time with little or no loss in optimality.

Combinational logic synthesis for LUT based field programmable gate arrays

“…A more recent MILP approach by Chowdhary and Hayes [1995] uses the mixed integer linear programming formulation, which can be applied to area minimization as we introduced in Section 4.3.2, as well as other objectives such as depth minimization with area constraint. The MILP formulation was solved using branch-and-bound enumeration.…”

“…Both node selection and node covering problems can be formulated in an integer linear programming 9 formulation as recently proposed in Chowdhary and Hayes [1995]. Each node v is associated with a variable e(v) ʦ {0, 1}, where e(v) ϭ 1 if and only if v is visible in the mapping solution; and with a variable s(v), indicating the maximum input size of an LUT containing v. Moreover, each pair of nodes u and v where some fanouts of u reconverge at v, are associated with a variable r (u, v).…”

“…The numbers of variables and constraints may reach O(n 2 ) for a network of n nodes, due to the existence of a possibly quadratic number of reconvergent paths. In Chowdhary and Hayes [1995] the integer linear programming problem is solved using branch-and-bound for implicitly enumerating the values of integer variables. At each step of enumeration, a subset of variables is fixed and other variables are relaxed to real valued variables.…”

An efficient algorithm for finding the minimal-area FPGA technology mapping

“…For the area minimization objective, if duplication of gates is allowed, the existing algorithms can be classified into three categories: (1) those using enumeration methods including Chortle [Francis et al 1990], Chortle-crf [Francis et al 1991], MIS-pga [Murgai et al 1990], MIS-pga (new) [Murgai et al 1991], Vismap [Woo 1991], and MILP [Chowdhary and Hayes 1995] algorithms; (2) those using heuristic algorithms, for example, the Level-Map algorithm [Farrahi and Sarrafzadeh 1994], and the CutMap algorithm [Cong and Hwang 1995] etc. ; and (3) those combining decomposition with mapping algorithms including the Xmap algorithm [Karplus 1991], the FGSyn algorithm [Lai et al 1994], the TechMap algorithm [Sawkar and Thomas 1992], the method developed by Lehman et al [1997], and the SLDMap algorithm [Chen and Kong 2001].…”

Clip

“…While ILP has sometimes been perceived as having excessive computational requirements, we show that it is practical for the 2D cell layout problem. Recent research has also successfully applied ILP to several other practical CAD problem [Chowdhary and Hayes 1995;Kim and Kang 1995;Maulik 1995] CLIP proceeds in two stages: First, an ILP model that aims at maximizing diffusion sharing among transistors and minimizing vertical inter-row connections determines a 2D placement of minimum width W cell . Then, a second ILP model generates a 2D layout that has width W cell and minimizes the cell height, measured in terms of the total number of horizontal routing tracks required.…”