A general decomposition strategy for verifying register renaming

Abstract

This paper describes a strategy for verifying data-hazard correctness of out-of-order processors that implement register-renaming. We define a set of predicates to characterize register-renaming techniques and provide a set of model-checking obligations that are sufficient to guarantee that a register-renaming technique satisfies data-hazard correctness. We demonstrate how two register renaming techniques (retirement-register-file and dual-RAT) instantiate our predicates, and present model checking results for the Dual-RAT technique, which is based on the Intel Pentium R 4 processor.

A framework for systematic validation and debugging of pipeline simulators

“…For example, Levitt and Olukotun [1997] used formal verification for pipeline implementation to verify a design against itself. There have been efforts to verify formally almost all the features of a pipeline, for example, register renaming [Shehata et al 2004], speculative execution [Arons and Pnueli 2000;Sawada and Hunt 1998], out-of-order execution [Arons 2004;Damm and Pnuelli 1997], and Tomasulo's algorithm [Arons and Pnueli 1999;McMillan 1998]. However, these methods require detailed specifications of architectures as input to the verifier.…”