2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation 2008
DOI: 10.1109/icsamos.2008.4664840
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A general model of concurrency and its implementation as many-core dynamic RISC processors

Abstract: A general model of concurrency and its implementation as many-core dynamic RISC processors Bernard, T.A.M.; Bousias, K.; Guang, L.; Jesshope, C.R.; Lankamp, M.; van Tol, M.W.; Zhang, L. General rightsIt is not permitted to download or to forward/distribute the text or part of it without the consent of the author(s) and/or copyright holder(s), other than for strictly personal, individual use, unless the work is under an open content license (like Creative Commons). Disclaimer/Complaints regulationsIf you belie… Show more

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Cited by 14 publications
(6 citation statements)
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“…Its success can be shown from the good scalability and flexibility over a range of benchmarks running on the Micro Grid [Bousias et al 2006;Bernard et al 2008;Yang et al 2011;]. However, It may be injected into another L2 cache with empty slot or matched tag, or retired to DRAM.…”
Section: Cost Of the Coherence Protocolmentioning
confidence: 97%
“…Its success can be shown from the good scalability and flexibility over a range of benchmarks running on the Micro Grid [Bousias et al 2006;Bernard et al 2008;Yang et al 2011;]. However, It may be injected into another L2 cache with empty slot or matched tag, or retired to DRAM.…”
Section: Cost Of the Coherence Protocolmentioning
confidence: 97%
“…SVP [3], [4], [5] is a multi-core architecture and programming model that The first and the last thread in the previous process reads and writes values from and to the shared memory. The shared memory is used for the storage of scalar and array data.…”
Section: The Svp Modelmentioning
confidence: 99%
“…Cycle-accurate models: The design of the architecture stays fluid through simulation in order to realize a validated system in silicon and to provide further optimizations in the silicon chip. The most commonly used simulation technique in academia and industry is the detailed, event-driven simulation of all the components of the architecture [7] [19]. Detailed simulation is generally the first step in the design process of an architecture soon after pen and paper model and analytical models.…”
Section: Uddinmentioning
confidence: 99%