A generalized methodology for lower-error area-efficient fixed-width multipliers

Van, Lan-Da; Lee, Sung-Huang

doi:10.1109/iscas.2002.1009778

Cited by 5 publications

References 8 publications

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Adaptive Low-Error Fixed-Width Booth Multipliers

Song¹,

Van²,

Kuo³

2007

IEICE Transactions on Fundamentals of Electronics, Communicatio

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In this paper, we propose two 2's-complement fixed-width Booth multipliers that can generate an n-bit product from an n-bit multiplicand and an n-bit multiplier. Compared with previous designs, our multipliers have smaller truncation error, less area, and smaller time delay in the critical paths. A four-step approach is adopted to search for the best errorcompensation bias in designing a multiplier suitable for VLSI implementation. Last but not least, we show the superior capability of our designs by inscribing it in a speech signal processor. Simulation results indicate that this novel design surpasses the previous fixed-width Booth multiplier in the precision of the product. An average error reduction of 65-84% compared with a direct-truncation fixed-width multiplier is achieved by adding only a few logic gates.

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Adaptive Low-Error Fixed-Width Booth Multipliers

Song¹,

Van²,

Kuo³

2007

IEICE Transactions on Fundamentals of Electronics, Communicatio

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A Low-Error and Area-Time Efficient Fixed-Width Booth Multiplier

Song

Van

Huang

et al.

2003 46th Midwest Symposium on Circuits and Systems

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In this paper, we develop a new methodology for designing a lower-error and area-time efficient 2 s-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit product. By properly choosing the generalized index and binary thresholding, we derive a better error-cojmpensation bias to reduce the truncation error. Since the proposed errorcompensation bias is realizable, the constructing low-error fixedwidth Booth multiplier is area-time efficient for VLSI implementation. Finally, we successfully apply the proposed fixed-width Booth multiplier to speech signal processing. The simulation results show that the perfoirnance isi stiperior to that using the direct-truncation fixed-width Booth multiplier.

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A generalized methodology for low-error and area-time efficient fixed width booth multipliers

Song

Van

Huang

et al.

The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.

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In this paper, we extend our generalized methodology for designing a lower-error and area-time efficient 2's-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit product. The generalized methodology involving three steps results in several better error-compensation biases. These better error-compensation biases can be mapped to low-error fixed-width Booth multipliers suitable for VLSI implementation. Finally, we successfully apply the proposed fixed-width Booth multipliers to speech signal processing. The simulation results show that the performance is superior to that using the direct-truncation fixed-width Booth multiplier.

show abstract

A generalized methodology for lower-error area-efficient fixed-width multipliers

Cited by 5 publications

References 8 publications

Adaptive Low-Error Fixed-Width Booth Multipliers

Adaptive Low-Error Fixed-Width Booth Multipliers

A Low-Error and Area-Time Efficient Fixed-Width Booth Multiplier

A generalized methodology for low-error and area-time efficient fixed width booth multipliers

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