A Generalized Workflow for Creating Machine Learning-Powered Compact Models for Multi-State Devices

Abstract

The predictive capability of existing physical descriptions of multi-state devices (e.g., oxide memristors, ferroelectrics, antiferroelectric, etc.) cannot be fully leveraged in circuit simulations due to practical limitations regarding the complexity of compact models. We attempt to circumvent this issue by adopting a machine-learning (ML) -based approach to develop a compact model that retains the full physical description of these devices. MLbased modeling approaches have garnered immense interest in recent years and have already been successfully utilized in making models for several novel devices. A known hurdle for ML-based compact modeling is the need for large amount of experimental data to properly train the model. We propose a method to simulate additional data by duplicating the data and adding Gaussian Noise to the duplicates. We propose a generalized framework to -(i) facilitate efficient training of ML-based device models, (ii) conduct seamless conversion to Verilog-A model, and (iii) interface with industry-standard circuit simulators (HSPICE, SPECTRE, etc.). We demonstrate the capabilities of our framework using the hafnium oxide (HfOx) memristor as a test device. As the source of the training data, we use a physical model that unifies detailed atomic-level descriptions with self-consistent evaluation of electronic transport. In addition, we test our model with experimental data for multiple memristor samples and repeated cycles of the same sample. Our ML-based framework prepares a circuit-compatible compact model to facilitate system-level simulations. With our model, we achieve a root mean squared error (RMSE) of 0.000863 and an R 2 of 0.977371 on our testing data.

Machine learning-powered compact modeling of stochastic electronic devices using mixture density networks

“…Here, the value represents the percentage of variance in the switching probability explained by the model. We can compare this to a deterministic neural network such as a multiplayer perception (MLP), which has been proposed for compact modeling by several pervious works 6 , 7 , 10 . To do this, we can train the model to predict the threshold gate current for a given bias voltage ( ).…”

“…This finalized Verilog-A model is compatible with various circuit simulators that support Verilog-A models, such as HSPICE or Spectre. This process is derived from Hutchins et al 10 .…”

“…In the pursuit of greater accuracy and ease of implementation in electronic circuit simulations, a significant leap has been taken by incorporating machine learning methodologies into compact modeling 5 – 10 . While various machine learning-based compact models have emerged, these models, thus far, have failed to address the implications of stochastic behavior in electronic devices.…”

Machine Learning-Based Compact Model Design for Reconfigurable FETs

“…Machine Learning Based Compact Models: NN based Machine learning approaches for semiconductor devices have been presented recently. Hutchins et al ( [18]) describe the projection of a HfOx memristor to a neural network with 3 hidden layers. Raju et al ( [19]) show how noise augmentation on TCAD data prevents overfitting of a Schottky diode model.…”

“…The target neural network structure of the linear model is an MLP as described in subsection III-A with 3 hidden layers, 20 neurons each. The number of hidden layers follows the demonstrations of Hutchins et al [18] and Tung et al [28], which propose semiconductor models with 3 hidden layers. All hidden layers within a neural network are sized equally and the respective size parameters for logarithmic and linear neural network are determined by manual hyperparameter search.…”