A generative approach to Universal Cross Assembler design

The Java TM programming language is primarily used for platform-independent programming. Yet it also offers many productivity, maintainability and performance benefits for platform-specific functions, such as the generation of machine code.We have created reliable assemblers for SPARC TM , AMD64, IA32 and PowerPC which support all user mode and privileged instructions and with 64-bit mode support for all but the latter. These assemblers are generated as Java source code by our extensible assembler framework, which itself is written in the Java language. The assembler generator also produces javadoc comments that precisely specify the legal values for each operand.Our design is based on the Klein Assembler System written in Self. Assemblers are generated from a specification, as are table-driven disassemblers and unit tests. The specifications that drive the generators are expressed as Java language objects. Thus no extra parsers are needed and developers do not need to learn any new syntax to extend the framework for additional ISAs.Every generated assembler is tested against a preexisting assembler by comparing the output of both. Each instruction's test cases are derived from the cross product of its potential operand values. The majority of tests are positive (i.e., result in a legal instruction encoding). The framework also generates negative tests, which are expected to cause an error detection by an assembler. As with the Klein Assembler System, we have found bugs in the external assemblers as well as in ISA reference manuals.Our framework generates tens of millions of tests. For symbolic operands, our tests include all applicable predefined constants. For integral operands, the important boundary values, such as the respective minimum, maximum, 0, 1 and -1, are tested. Full testing can take hours to run but gives us a high degree of confidence regarding correctness.

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“…Other specification language based assembler generators are also described in [22], [4] and similar publications about cross assemblers.…”

Section: Related Workmentioning

confidence: 99%

The Project Maxwell assembler system

Mathiske

Simon

Ungar

2006

Proceedings of the 4th International Symposium on Principles and Practice of Programming in Java - PPPJ '06

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“…Most assembler generators reported in the literature [6,12,13] use Lex and Yacc for both ADL and assembly language parser generation. Besides its inherent limitation to LALR(1) syntactic analysis [11], Yacc does not have a co-validation mechanism between language and grammar.…”

Section: B Parser Generation Enginesmentioning

confidence: 99%

Automatically Retargetable Pre-Processor and Assembler Generation for ASIPs

Taglietti

Filho

Casarotto

et al.

The 3rd International IEEE-NEWCAS Conference, 2005.

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During design space exploration, alternative CPUs are evaluated for an envisaged SoC, thereby requiring fast CPU models and efficient code generation tools. Candidate CPUs may be general-purpose processors, DSPs, micro-controllers or ASIPs. The ASIP is a particularly challenging alternative: since instruction-set architecture (ISA) tailoring is allowed, an ASIP cannot rely on pre-existent code generation tools. Each target ISA requires a new tool chain. Therefore, an automatically retargetable tool chain is mandatory. This paper focuses on a couple of tools from such a chain: pre-processor and assembler. It proposes robust and efficient techniques allowing retargetability through automatic tool generation from a given target ISA, which is formally described by Architecture Description Language (ADL) constructs. Tool robustness results from formal techniques based on context-free grammars. Tool efficiency evidence is provided by experiments targeting three CPUs: MIPS, PowerPC 405 and PIC 16F84.

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