We discuss the problem of simultaneously scheduling, binding and routing a given data flow graph to a coarse-grain architecture consisting of identical processing elements (PEs) that are connected by a nearest-neighbour mesh-like interconnection network.While there are heuristics trying to solve this problem, we develop the first exact method based on integer linear programming. This allows us to achieve provably optimal solutions for two different objective functions, for small to medium instances. In addition, we describe a heuristic that seems to outperform all other known heuristics.

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The high degree of freedom in the design of coarse-grained reconfigurable arrays imposes new challenges on their description and modeling. In this paper, we introduce an architecture description language targeted to describe coarse-grained reconfigurable architecture templates. It comprises innovative key features to allow fast modeling and analysis of such architectures, i.e.: representation of processing element array (ir)regularities, and flexible and concise description of interconnection network. We demonstrate that the proposed language enables a formal validation of the described template, and it eases the analysis and estimation of hardware costs earlier in the design phase. Finally, we show how we automatically generate a SystemC-based simulator of the described architecture. Our results suggest that the semantic and technical innovations of the proposed architecture description language may have a positive impact on the productivity of the design phase.Index Terms-Custom instruction, domain specific architecture, hardware description languages, reconfigurable hardware.

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Resumo-O uso de chips de FPGA vem crescendo nas últimas duas décadas devido a sua capacidade de reconfigurac ¸ão pelo usuário e os avanc ¸os de ferramentas de prototipagem rápida. Sendo assim, este artigo apresenta o projeto de uma func ¸ão exponencial de alto-desempenho para um chip FPGA (Field Programmable Gate Array) da Xilinx, utilizando a ferramenta de prototipagem rápida Xilinx System Generator for DSP T M e uma placa de desenvolvimento da Nallatech XtremeDSP Kit-IV com uma Virtex-4SX. Este trabalho mostra uma forma eficiente de implementac ¸ão em hardaware da func ¸ão exponencial visando o uso em sistemas de comunicac ¸ões.