Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures

Brenner, Janina; Veen, Jan C. van der; Fekete, Sándor P.; Filho, J. Oliveira

doi:10.1109/fpl.2006.311262

Cited by 15 publications

(5 citation statements)

References 8 publications

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“…They are also frequently used to compare results from heuristic-based methods. The contribution presented in [10] is particularly in line with our work because an ILP formulation for solving optimally and simultaneously the mapping, routing and scheduling of a given data flow graph on a coarse-grain architecture is presented. The main difference, apart the formulation type, resides in the targeted architecture model, which consists of homogeneous processing elements and mesh-like interconnection network.…”

Section: Related Workmentioning

confidence: 67%

Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture

Raffin¹,

Wolinski

Charot

et al. 2012

International Journal of Embedded and Real-Time Communication Systems

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International audienceThis article presents an integrated environment for application scheduling, binding and routing used for the run-time reconfigurable, operator based, ROMA multimedia architecture. The environment is very flexible and after a minor modification can support other reconfigurable architectures. Currently, it supports the architecture model composed of a bank of single (double) port memories, two communication networks (with different topologies) and a set of run-time functionally reconfigurable non-pipelined and pipelined operators. The main novelty of this work is simultaneous solving of the scheduling, binding and routing tasks. This frequently generates optimal results, which has been shown by extensive experiments using the constraint programming paradigm. In order to show flexibility of our environment, we have used it in this article for optimization of application scheduling, binding and routing (the case of the non-pipelined execution model) and for space exploration (case of the pipelined execution model)

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Section: Related Workmentioning

confidence: 67%

Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture

Raffin¹,

Wolinski

Charot

et al. 2012

International Journal of Embedded and Real-Time Communication Systems

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“…A solution adopted in many cases is to let the control flow managed by a host processor. But this reduces greatly the pos- Spatial mapping [23], [30], [31] GA [19] SA [32], [33] ILP [23], [34], [35] Temporal mapping [12], [16], [26], [36]- [40] SA [22] ILP [41] B&B [42] CP [43] SAT [17] SMT [44] Binding [14], [24], [28], [45]- [47] QEA [48] SA [30], [49], [50] ILP [15], [48] Scheduling [24], [28], [36], [46], [48], [50]- [52] ILP [15], [53] sibilities to use the CGRA and increases the communication overhead, loosing sometimes the benefit of the acceleration provided by the CGRA. Another approach is to provide the CGRA with extra hardware features to support the control flow.…”

Section: B Control-flow Mappingmentioning

confidence: 99%

Twenty Years of Automated Methods for Mapping Applications on CGRA

Martin

2022

2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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Coarse-GrainedReconfigurable Architectures (CGRAs) emerged about 30 years ago. The very first CGRAs were programmed manually. Fortunately, some compilation approaches appeared rapidly to automate the mapping process. Numerous surveys on these architectures exist. Other surveys also gather the tools and methods, but none of them focuses on the mapping process only. This paper focuses solely on automated methods and techniques for mapping applications on CGRA and covers the last two decades of research. This paper aims at providing the terminology, the problem formulation, and a classification of existing methods. The paper ends with research challenges and trends for the future.

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“…Our tools for placement and routing are currently in a rather experimental state [2]. Since these steps influence the performance results significantly, we use NEC's DRP and its stable tool chain for the performance evaluation.…”

Section: Evaluation Approachmentioning

confidence: 99%

Optimization of Area and Performance by Processor-Like Reconfiguration

Oppold

Eisenhardt

2007

2007 IEEE International Parallel and Distributed Processing Symposium

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It is well known that the area efficiency of a digital circuit can be improved by reconfiguration due to the reuse of resources. In this paper, we show that this benefit can be achieved for a wide range of applications if the reconfiguration can take place within each clock cycle, and we quantify the benefit by area estimations from a synthesizable architecture model. Although reconfiguration typically involves a decrease of performance, we show how performance can actually be increased by redirecting communication through the time domain. This increase is quantified by estimations from a silicon-proven commercial architecture and its associated compiler.

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Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures

Cited by 15 publications

References 8 publications

Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture

Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture

Twenty Years of Automated Methods for Mapping Applications on CGRA

Optimization of Area and Performance by Processor-Like Reconfiguration

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